Device and method for controlling multiple DMA tasks

Details Device and method for controlling multiple DMA tasks Device and method for controlling multiple DMA tasks

2011-04-19

2011-04-19

Sorrell, Eron J (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S024000, C710S025000

Reexamination Certificate

active

07930444

ABSTRACT:
A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.

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Non-Final Office mailed Apr. 30, 2010 for U.S. Appl. No. 11/994,276, 24 pages.
Final Office mailed Aug. 31, 2010 for U.S. Appl. No. 11/994,276, 17 pages.

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