Device and method for controlling data transfer

Details Device and method for controlling data transfer Device and method for controlling data transfer

2007-02-27

2007-02-27

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S033000, C710S048000, C710S052000

Reexamination Certificate

active

10762667

ABSTRACT:
A data transfer control device and method is devoted to control data transfer (i.e., DMA transfer) between a main memory whose storage capacity is arbitrarily set and a buffer memory (e.g., a FIFO memory) incorporated in a peripheral module, wherein a first register is arranged to store a first value representing a first number of times for transferring m-bit data to suit the storage capacity of the buffer memory, and a second register is arranged to store a second value representing a second number of times for transferring m-bit data to match the amount of transferring data stored in the main memory. A controller is arranged to control transferring of m-bit data based on the first value while controlling writing operations for the buffer memory. It determines the timing to output an interrupt signal to a CPU managing the main memory on the basis of the second value.

REFERENCES:
patent: 5857114 (1999-01-01), Kim
patent: 6816921 (2004-11-01), Jahnke et al.
patent: 2003/0172229 (2003-09-01), Takasugi et al.
patent: 2004/0073721 (2004-04-01), Goff et al.
patent: 2005/0210221 (2005-09-01), Mitsuishi
patent: 05-276221 (1993-10-01), None
patent: 2000-322375 (2000-11-01), None
Japanese Patent Office, “Notice of Rejection in connection with Japanese Patent Application No. 2003-017681,” (Sep. 12, 2006).

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