Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-11-02
2001-03-20
Yoo, Do (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S230060, C365S233100
Reexamination Certificate
active
06205516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for controlling a data storage device, such as DRAM (dynamic random access memory) and the like, and to a method for controlling the data storage device which is connected to a CPU and the like in a data processing system.
2. Description of Related Art
DRAM is generally used as a main memory for a microprocessor or the like computer. Efforts have been made to increase the capacity of this DRAM in order to improve the performance of the entire computer systems.
In recent years, there has been increasing demand not only to increase the memory capacity, but also to increase the data transfer rate of the DRAM in accordance with increase in the speed of microprocessors. This has led to the development of various types of high speed DRAM.
Representative examples of the high-speed DRAM includes: DRAM provided with high-speed access mode called “fast page mode”. DRAM provided with extended data out (EDO) page mode; DRAM provided with burst extended data out (EDO) page mode; synchronous DRAM (SDRAM); and Rambus DRAM. The SDRAM and Rambus DRAM are synchronous DRAMs, while the fast page mode DRAM, the EDO-DRAM, and the burst EDO-DRAM are asynchronous DRAMs.
Recently, SDRAM is generally used as a main memory in a high performance machine such as a server computer. The SDRAM is now being used also in other several machines of personal use such as personal computers and personal printers.
The SDRAM is a high-speed DRAM that can operate in synchronization with a clock signal supplied to a computer such as a microprocessor. There has been realized such a high-speed SDRAM that can attain a high data transfer rate of 800 megabytes per second using a 64 bit wide data bus and a clock signal at frequency of 100 MHz.
In order to attain this high-speed operation, SDRAM is provided with an internal column address counter. The column address counter is mounted on a SDRAM chip. This internal address counter is used during a transfer mode called “burst mode”. When column address data is inputted, the column address counter counts up, from the inputted column address, a successive series of column addresses in synchronization with a clock signal, whereby data reading/writing operation can be executed on the successive series of addresses.
It is noted that a user can freely set burst length and CAS latency of the burst mode. The burst length is defined as the number of data to be serially inputted/outputted in synchronization with the clock signal. The CAS latency is defined as the number of clock cycles set after a column address strobe signal CAS is inputted until data is actually started being outputted. Thus, the system can be designed according to the user's desire.
SUMMARY OF THE INVENTION
In order to set the burst length and the CAS latency to the SDRAM, specific parameters have to be stored into an internal register called “mode register,” which is provided also on the SDRAM chip. Because SDRAM thus requires the special mode register setting operation, it is difficult to use SDRAM in general type systems.
In order to set the specific parameters into the mode register, a predetermined control signal is first inputted to the SDRAM so that an operation mode of SDRAM is set into a mode register setting mode. Then, specific parameter are stored into the mode register in the form of address data that is constructed from a combination of predetermined several bits. If address data for SDRAM is defined by twelve bits A
0
through A
11
, for example, CAS latency is set by three bits A
4
-A
6
, and the burst length is set by other three bits A
0
-A
2
. In order to perform the parameter setting operation, remaining high-order bits A
7
-A
11
have to be fixed to zero (0).
According to the contents of the parameters (burst length and/or CAS latency) to be set, however, the address data A
0
-A
11
may possibly indicate some address that could not be defined in the system. It becomes difficult to design a memory map and hardware construction of the entire system.
The present invention is attained to solve the above-described problems. An object of the present invention is therefore to provide a device and method for controlling a data storage device provided in a data processing system, in which a memory map can be easily designed and therefore the hardware can be easily constructed even when the data storage device is of a type, such as SDRAM, that sets a mode register with information in the form of address data.
In order to attain the above and other objects, the present invention provides a control device for controlling a data storage device of a type that receives address data indicative of a desired operation mode and that sets the desired operation mode in an operation mode setting portion provided thereto, the control device comprising: means for receiving; a control signal for setting an operation mode, address data indicative of an operation mode setting portion of the data storage device, and command data indicative of a content of an operation mode desired to be set to the data storage device; means for judging whether or not the received address data indicates the operation made setting portion: means for, when the address data indicates the operation mode setting portion, producing specific address data indicating the desired operation mode based on the received command data and a specific control signal for setting the operation mode setting portion; and means for outputting, to the data storage device, the specific address data and the specific control signal, thereby causing the operation mode setting portion to be set with the desired operation mode.
According to another aspect, the present invention provides a control system, comprising: a data storage device including: a plurality of memory elements; means for storing designation information designating an operation mode of the data storage device; and means for controlling an operation of the data storage device in accordance with the designation information stored in the information storing means, the controlling means selecting a desired memory element indicated by memory element address data when the memory element address data and a memory element control signal are inputted, the controlling means extracting designation information from designation address data and storing the designation information to the information storage means when the designation address data and a designation control signal are inputted; a data processing device for writing process data to and reading process data from the selected memory element, the data processing device outputting original address data, an original memory control signal, an original designation control signal, and designation content data indicative of a desired operation mode; and a control device for controlling the data storage device, the control device being connected between the data storage device and the data processing device, the control device including: means for judging whether or not the original address data inputted from the data processing device indicates the information storage means; means for, when the original address data indicates the information storage means, producing the designation address data, including the designation information, based on the designation content data, which is outputted from the data processing device in correspondence with the original address data, and for producing the designation control signal based on the original designation control signal; means for, when the original address data indicates some memory element, producing the memory element address data based on the original address data and for producing the memory element control signal based on the original memory element control signal; and means for outputting, to the data storage device, the designation address data and the designation control signal when the designation address data and the designation control signal are produced, and for outputting, to the data storage device,
Brother Kogyo Kabushiki Kaisha
Namazi Mehdi
Yoo Do
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