Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2006-09-19
2006-09-19
Fleming, Fritz (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C709S233000, C709S234000, C710S060000
Reexamination Certificate
active
07111091
ABSTRACT:
The present invention proposes a device for controlling a stream of data packets, comprising: a buffer (2) adapted to receive a data packet stream from a data source (1) and to output said packet data stream with an output rate to a packet data communication network (7), a monitoring means (4) adapted to monitor a fill level of said buffer (2), a detection means (5) adapted to detect a fill level condition of said buffer (2), in which an incoming data packet has to be dropped, and adapted to control a dropping means (6) for dropping an incoming data packet upon detection of said fill level condition, and further comprising an output rate control means (5a, 8, 9, 10, 11) adapted to control an output rate adjusting means (3) which is adapted to adjust said output rate of said buffer (2), wherein said output rate control means, in response to said fill level condition detected by said detection means (5), issues a first control signal (5a) controlling said adjusting means (3) to increase a current output rate of said buffer to a predefined output rate, and said output rate control means, in response to each non-dropped data packet received after said detection by said detection means (2), issues a second control signal (11a) controlling said adjusting means (3) to decrease a currently adjusted output rate. The present invention also proposes a corresponding control method.
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patent: 5500689 (1996-03-01), Lam
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Patent Abstracts of Japan, vol. 017, No. 066, Feb. 9, 1993 & JP 04 274572.
Lakaniemi Ari
Räisänen Vilho
Fleming Fritz
Franklin, Jr. Richard B.
Squire, Sanders and Dempsey, LLP.
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