Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-08-21
2004-06-29
Bragdon, Reginald G. (Department: 2188)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S104000, C711S118000
Reexamination Certificate
active
06757840
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to semiconductor memory devices and, more specifically, to a cache tag that can be configured in accordance with a selected burst length.
2. State of the Art
Modern memory systems for personal computers and the like generally include a main memory that consists of approximately 32 Megabytes (MB) or more of Synchronous Dynamic Random Access Memory (SDRAM), a smaller but faster memory cache that usually consists of about 512 Kilobytes (KB) of Static RAM (SRAM), and an even smaller cache “tag” that usually consists of about 16 KB to 64 KB of SRAM. The role of the memory cache is to provide, for some data requests, faster access to the requested data than the main memory can provide, and the role of the cache tag is to help determine whether or not the requested data is stored in the memory cache.
In one cache architecture, a microprocessor requests data from the memory system by first presenting the address of the requested data on a private cache bus interconnecting the microprocessor, the memory cache, and the cache tag. The cache tag receives the address (or, more commonly, a portion thereof), selects one of its internal memory locations in accordance with the address (or a portion thereof), and then writes out address data stored at the selected memory location to the microprocessor via the private cache bus. At the same time, the memory cache also receives the address, selects one of its internal memory locations in accordance with the address, and writes out the data stored at the selected memory location to the microprocessor.
If the microprocessor determines that the address data written out by the cache tag matches the address of the requested data (or a selected portion thereof), then a “cache hit” has occurred. In this circumstance, the microprocessor uses the data output by the memory cache, since the occurrence of a cache hit indicates that this data is the correct data. Conversely, if the microprocessor determines that the address data written out by the cache tag does not match the address of the requested data (or a selected portion thereof), then a “cache miss” has occurred. In this circumstance, the microprocessor requests the data from the main memory, because the occurrence of a cache miss indicates that the data output by the memory cache is not the correct data.
Defects sometimes occur in a cache tag during the manufacturing process that prevent certain memory locations within the tag from functioning properly. If these defects cannot be repaired through conventional use of redundant elements, then the integrated circuit (IC) device that incorporates the defective tag is typically scrapped. There is, therefore, a need in the art for a device and method that can recover such devices for sale and subsequent use, thereby avoiding the need to scrap the devices.
SUMMARY OF THE INVENTION
A cache tag for use with a memory cache includes tag subarrays and status indicating elements (e.g., laser fuses, antifuses, flash memory cells, zero-ohm resistors) that indicate the functional status of the tag subarrays. Also, enabling circuitry selectively enables the tag subarrays in accordance with a selected burst length of the memory cache and the functional status of the tag subarrays as indicated by the status indicating elements. By increasing the burst length of the memory cache in order to reduce the number of tag subarrays needed for operation of the memory cache, and then disabling nonfunctional tag subarrays, a cache tag that typically would have been scrapped is, instead, recovered for sale and subsequent use.
In other embodiments of this invention, the cache tag described above is incorporated into an electronic system, a Static Random Access Memory (SRAM), a semiconductor memory device, and a semiconductor substrate (e.g., a semiconductor wafer).
In still another embodiment, a semiconductor memory device having a cache tag with nonfunctional tag subarrays is repaired by increasing the burst length of the memory device so the nonfunctional tag subarrays are not needed for operation of the memory device.
In yet another embodiment, the method described above is followed by selectively disabling the nonfunctional tag subarrays.
REFERENCES:
patent: 5301296 (1994-04-01), Mohri et al.
patent: 5729497 (1998-03-01), Pawlowski
patent: 5905996 (1999-05-01), Pawlowski
patent: 6067600 (2000-05-01), Pawlowski
patent: 6185149 (2001-02-01), Fujioka et al.
patent: 6526473 (2003-02-01), Kim
patent: 6549984 (2003-04-01), Patterson et al.
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