Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-19
2001-02-27
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C713S501000, C370S402000
Reexamination Certificate
active
06195720
ABSTRACT:
The present invention relates to a device and a method for communication between computer buses.
A computer bus is composed of a set of electrical lines which carry data, addresses, interrupt signals and control signals.
Generally there is a maximum or optimum number of components which can be connected to a given bus. When a computer system is composed of a higher number of components, a supplementary bus may be used to connect some components, this supplementary bus having to be connected to the initial bus by a component called a “bridge”. In the field of buses to the so-called “PCI” standard, inter-bus communication or interconnection has a hierarchical nature, that is to say one of the buses is referred to as primary and the other is referred to as secondary. By using, between these buses, a so-called “bridge” component, defined by the standard of the bus, the configuration of the components connected to the secondary bus and their access to the primary bus are controlled by the primary bus.
The bus known to persons skilled in the art by the name PCI (“Peripheral Component Interconnect”) is a bus for the interconnection of processors, peripheral controller components or memories.
A PCI to PCI bridge, as defined by the standard
“PCI to PCI Bridge Architecture Specification, Revision
1.0”, allows a connection between two PCI buses in order to perform transactions between a “master” on one PCI bus and a “slave” on the other PCI bus. A bridge therefore has two interfaces, each of them capable of being master or slave on the bus to which it is connected.
An inter-bus interconnection made with such a bridge has the following drawbacks, when there is a processor on each bus:
each component which has a direct interface with a PCI bus has configuration registers, the addresses of which are defined by the PCI standard. These configuration registers are read and then initialised by the processor present on the primary bus, called the “host” processor. On power-up, the processor present on the PCI bus starts a program for configuring the various peripherals present on the bus. This program may be the program called, by persons skilled in the art, BIOS (“Basic Input Output System”). This program is executed by means of an interface component placed between the processor and the PCI bus, a component which carries the configuration commands to the various components it recognises on the bus and on the buses present behind any “bridges”. These configuration commands are reads from and writes to various configuration registers and make it possible to allocate memory space or input/output space as well as interrupts according to requests from the various configurable components.
If a PCI to PCI bridge is present on the bus, it carries the data intended for the components present behind it, that is to say on the secondary PCI bus. When at least two buses are connected by a PCI to PCI bridge component and each bus is connected to a processor, each processor, through its bus interface component, attempts to initialise all the components present on its bus and on the bus present behind the PCI to PCI bridge. This therefore creates an initialisation conflict since each component undergoes two initialisations.
in order to communicate, the two processors must be able to access the memory present on the bus to which they are not directly connected. As a result of the bridge, the same addresses may be used for different memory registers on either side of the bridge. Consequently, the transactions can be performed between the two buses only when two different address registers are used on either side of the bridge.
the clocks of the two processors are asynchronous and it is often impossible to generate a processor clock with a bus clock. Furthermore, certain PCI to PCI bridges (for example, the component referenced 1960RP from the company formed under American law INTEL) have significant synchronisation constraints, which necessitates that all the clocks originate from the same source on each of the two buses.
The invention intends to remedy these drawbacks.
To this end, the present invention relates, according to a first aspect, to a device for communication between at least two asynchronous computer buses, characterised in that it has:
at least one intermediate storage means adapted to be accessed in read and/or write mode at at least two different frequencies,
for each computer bus, an adapter for interfacing between the said computer bus and a storage means, having an adapter memory and two bidirectional ports, one of the said bidirectional ports being connected to the said computer bus and the other bidirectional port being connected to the said storage means,
each intermediate storage means thus being capable of being accessed in write and/or read mode by means of each of the said computer buses and the interface adapter which is associated with the said computer bus.
Thus each storage means can be accessed in write mode and read mode by each computer bus, without it being necessary for these computer buses to operate synchronously or even at the same frequency, without it being necessary for the addresses used to access the storage means to be necessarily identical, and without a joint initialisation of the components on the different computer buses being necessary.
The architectures of the electronic or computer systems connected to the different computer buses can therefore be designed independently and operate in an independent manner, apart from the phases of communication between these buses.
According to particular characteristics, one of the storage means comprises a dual port random access memory, each port of the said random access memory being connected to one of the interface adapters.
By virtue of these provisions, two computer buses can have access to one of the ports of each dual port memory.
According to particular characteristics, one, at least, of the storage means comprises a random access memory in which the access to the data is made in the same order in read mode as in write mode, the input of the said random access memory being connected to one of the local ports and the output of the said memory being connected to another local port.
Preferentially, one, at least, of the storage means comprises two random access memories in which the access to the data is made in the same order in read mode as in write mode, the input of a first one of the said random access memories and the output of a second one of the said random access memories being connected to one of the local ports, on the one hand, and the output of the first one of the said random access memories and the input of the second one of the said random access memories being connected to another local port, on the other hand.
By virtue of each of these provisions, the writing and reading of data can be performed at high speed, the reading and writing in FIFO type memories, which correspond to the random access memories mentioned above, being particularly faster than in addressable memories.
According to particular characteristics, one, at least, of the adapter memories has an interrupt and/or address register which are assigned to it for operation of the adapter having the said memory, in relation with the computer bus to which it is connected.
By virtue of these provisions, the communication means according to the invention is considered, for its operation in relation with the computer bus connected to the said adapter, as a peripheral.
According to particular characteristics, two, at least, of the adapters are adapted to operate in direct memory access mode.
By virtue of these provisions, high-speed transfers can be performed using the said adapters in direct memory access mode.
According to a second aspect, the invention relates to a method of communication between at least two asynchronous computer buses, characterised in that it includes:
a step of storing in an intermediate storage means adapted to be accessed in write mode, by means of a first computer bus associated with a first interface adapter having an
Abiven Anne
Accarie Jean-Paul
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Ray Gopal C.
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