Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-03-28
2006-03-28
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C710S068000, C710S120000, C710S065000, C711S171000, C711S172000, C711S105000
Reexamination Certificate
active
07020759
ABSTRACT:
In a device and a method associating information concerning first memory cells and second memory cells of a memory element with an external memory, with each address of the memory element having a first predetermined number of memory cells associated therewith and each address of the external memory having a second number of memory cells associated therewith that is greater than said first predetermined number, and with said second predetermined number of memory cells on each address of the external memory being adapted to be subdivided into a first group of memory cells and a second group of memory cells, an input receives the information concerning said first and second memory cells. The information concerning first memory cells is assigned to the first group of memory cells in the external memory, and the information concerning the second memory cells is associated to the second group of memory cells in the external memory. Via an output adapted to be connected to the external memory, the information concerning the memory cells of the memory element is output to the associated group in the external memory.
REFERENCES:
patent: 5768546 (1998-06-01), Kwon
patent: 6237069 (2001-05-01), Fan
Namazi Mehdi
Padmanabhan Mano
Stomer Werner H.
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