Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
2000-08-29
2004-04-06
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S223000, C712S226000, C712S229000, C708S525000
Reexamination Certificate
active
06718459
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a device and method for arithmetic processing that executes instructions according to, for example, a microprogram and then selectively performs a predetermined arithmetic and logic operation such as rounding or saturation, to instruction-execution results.
Conventionally, there are arithmetic processing devices for the purpose of numerical arithmetic operations. The arithmetic processing device is configured of a numerical arithmetic section for executing a numerical arithmetic operation according to a statement described with a program and a register group for temporarily storing an input value to the numerical arithmetic section or the arithmetic result. Numerical values are exchanged via the register group.
In that type of arithmetic processing devices, a long data length is set in the numerical arithmetic section to improve the arithmetic accuracy. For that reason, when the numerical arithmetic section stores an arithmetic result to the memory or outputs it to external circuits, a predetermined process is carried out to shorten the data length. The so-called rounding process of rounding the lower bits of an arithmetic result or the so-called saturation process of saturating to a value by discarding the upper bits when an arithmetic result exceeds a predetermined value is well known as the predetermined process.
For that reason, the above arithmetic processing device generally contains a processing section and the so-called mode register. The processing section performs a predetermined process such as rounding or saturation, when the register group stores an arithmetic result from the numerical arithmetic section. The so-called mode register sets a flag which designates whether or not a predetermined process such as rounding is performed to the arithmetic result of the numerical arithmetic section.
Whether or not the above special process is needed to carry out to an arithmetic result of the numerical arithmetic section is defined by a program describing a series of process procedures. If necessary, “1”, for example, is written as a flag for the mode register. The flag to the mode register is rewritten every time the special process is performed.
In a program, for example, for a microprocessor, an instruction of executing a saturation process to an arithmetic execution result and an instruction of executing no saturation process may be alternately performed. In such a case, it is required to add the statement that resets a flag of the mode register for each instruction in each process on a program. The problem is that adding a statement leads to increasing the code size of the program and the number of execution steps so that the volume of the program is expanded.
SUMMARY OF THE INVENTION
The objective of the present invention is to solve the above-described tasks.
Furthermore, the objective of the invention is to provide an arithmetic processing device and method that can suppress an increase of the volume of a program describing a series of numerical arithmetic execution procedures even when a predetermined process is intermittently repeated to an instruction execution result.
In order to overcome the above mentioned problems, an arithmetic processing device of the present invention comprises a first register group (for example, a constituent element corresponding to the register group
40
, to be described later) for storing an instruction execution result (for example, a factor corresponding to the arithmetic result A of the numerical arithmetic circuit
50
, to be described later) executed according to a program which describes a series of procedures. A predetermined arithmetic and logic operation (for example, a constituent element corresponding to a specific process of the specific processing circuit
60
, to be described later) is selectively performed to said instruction execution result when the first register group stores the instruction execution result. The arithmetic processing device further has a second register (for example, a constituent element corresponding to the mode register
20
, to be described later) arranged corresponding to the first register group, for setting a flag specifying whether or not the arithmetic and logic operation is performed to an instruction execution result to be stored in a register including in the first register group specified on the program.
In the configuration of the arithmetic processing device, a flag designating whether to perform a predetermined arithmetic and logic operation to an instruction execution result is set to the second register. The bit of the second register corresponds to the first register. When a register in the first register group, to which an instruction execution result is stored, is designated on a program, whether to perform a predetermined process to the instruction execution result is determined according to the flag set to a bit of the second register corresponding to the designated register. In other words, if a flag is previously set to the second register, the presence or absence of a predetermined arithmetic and logic operation is determined by selecting a register, that is, a destination storing the instruction execution result. Therefore, it is unnecessary to vary a flag to designate whether to perform a predetermined arithmetic and logic operation on the program every operation. As a result, the statement on the program for setting a flag can be reduced.
Moreover, according to the present invention, an arithmetic processing device, wherein an instruction is executed according to a program which describes a series of procedures and a predetermined arithmetic and logic operation (for example, a constituent element corresponding to a specific process of the specific processing circuit
60
, to be described later) is selectively performed to the instruction execution result (for example, a factor corresponding to an arithmetic result A of the numerical arithmetic circuit
50
, to be described later), comprises a program storage section (for example, a constituent element corresponding to the program memory
10
, to be described later) for storing said program; an instruction execution section (for example, a constituent element corresponding to the numerical arithmetic circuit
50
, to be described later) for executing an instruction described in said program; a first register group (for example, a constituent element corresponding to the register group
40
, to be described later) for storing an instruction execution result from said instruction execution section; an arithmetic processing section (for example, a constituent element corresponding to the specific processing circuit
60
, to be described later) for performing a predetermined arithmetic and logic operation of said instruction execution result; a second register (for example, a constituent element corresponding to the mode register
20
, to be described later) arranged corresponding to said first register, for designating whether or not said predetermined arithmetic and logic operation is performed, to said instruction execution result of said instruction execution result; and a control section (for example, a constituent element corresponding to the decoder
30
, to be described later) for controlling said arithmetic and logic operation to said instruction execution result, by referring to a flag (for example, a constituent element corresponding to the flag set to the bits MR
0
to MR
7
of the mode register
20
, to be described later) set to said second register corresponding to registers (for example, a constituent element corresponding to the registers MR
0
to MR
7
, to be described later) forming said first register group designated on said program when said instruction execution result is stored in said first register group, said register acting as a register storing said instruction execution result.
According to the above configuration of the arithmetic processing device, when an instruction execution result is stored into the first register group, the con
NEC Electronics Corporation
Pan Daniel H.
Scully Scott Murphy & Presser
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