Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-01
2003-05-27
Ng{haeck over (o)}, Ng{haeck over (a)}n V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S362000
Reexamination Certificate
active
06570226
ABSTRACT:
REFERENCE TO RELATED APPLICATIONS
This application claims priority benefits to European Patent Application Number 99870110.6 filed on Jun. 1, 1999.
FIELD OF THE INVENTION
The present invention is related to a semiconductor device and a circuit for electrostatic discharge and overvoltage protection applications.
BACKGROUND OF THE INVENTION
Electronic devices and circuits are to be protected against damage arising from electrostatic discharge pulses, current transients or overvoltage levels. Protection devices or circuits using silicon controlled rectifier structures (SCR) are known in the art. SCR devices were applied frequently as an efficient electrostatic discharge protection clamp. These devices are made such that as a result of electrostatic discharge (ESD) pulses, current transients or overvoltage levels, an n-p-n-p thyristor structure is triggered thereby ensuring the clamping of the ESD-pulses, and snapback of the device to very low holding voltages. These devices furthermore are such that this absorption of electrostatic discharge pulses, current transients or overvoltage levels leads to low power dissipation after triggering. Examples of such SCR devices are disclosed in the U.S. Pat. Nos. 5,072,273, 5,343,053 and 5,663,860.
A cross-section of a prior art classical SCR-device is shown on FIG.
1
. The SCR-device is fabricated in a semiconductor substrate
12
of a p-type conductivity with a n-well
11
therein. In the figure, the pad connection
17
is connected to both the n-well contact region
13
and a p+-region
14
inside the n-well. The ground is connected to the p-substrate contact region
16
and an n+-region
15
inside the p-substrate
12
. An equivalent circuit schematic is shown in FIG.
2
. It comprises a parasitic pnp
299
and a parasitic npn transistor
200
that are connected. The npn-transistor
200
consists of the n-well/p-substrate
+region, whereas the pnp-transistor
299
consists of the p+-region
-well/p-substrate.
In normal operating conditions, the SCR-device is off. When a positive ESD-pulse is applied at the pad, the n-well
11
to p-substrate
12
diode
11
/
12
is reverse biased, until it goes into breakdown. This typically happens at voltages on the order of 40-50V. Once the n-well/substrate diode is in breakdown, electron-hole pairs are generated in the space-charge region of this diode. The holes are flowing to the p-substrate contact
16
, whereas the electrons are flowing to the n-well contact
13
. Due to the substrate resistance Rsub, the p-base of the parasitic npn transistor
200
is charging up, and when the base voltage is becoming higher than 0.7V, this npn parasitic transistor is triggered. At about the same time, the pnp transistor is triggered due to the charging up phenomenon, and via a positive feedback mechanism, the device is latched into a low impedance state, with a low holding voltage of typically 2-3 Volt, or in some applications 3-4V, and a low series resistance of typical a few Ohm, which leads to very low power dissipation and high ESD-thresholds.
The problem of most of the classical SCR devices is that the trigger voltage at which the device goes into the low-impedance on-state is quite high, typically 50V, which is too high for normal low-voltage technologies. In order to allow the use of SCR-devices but avoid the high trigger voltages, a so-called low-voltage triggered SCR (LVTSCR) has been proposed. A cross section of the LVTSCR is shown on
FIG. 3
, and an equivalent circuit schematic is shown on FIG.
4
. In this protection device, an n+region
39
is implanted at the edge between the n-well
31
and the p-substrate
32
. The n+-region/p-substrate junction will go into breakdown at a lower voltage, typical 13-14V, in this way lowering the triggering voltage of the SCR. The n+-region can be separated from the n+region in the p-substrate either by a field oxide or by a poly-gate (
395
, shown in FIG.
3
). In the latter case, the gate of the parasitic nMOS is connected to the ground, as is shown on
FIGS. 3 and 4
. This device is well suited to protect technologies with normal operating voltages.
AIMS OF THE INVENTION
The classical SCR protection devices are typically suited for high voltage applications, whereas the LVTSCR structure is frequently used for normal operating voltage applications. For some applications, however, the low trigger voltage (for instance of 14V) for an LVTSCR is too low, whereas the high trigger voltage (for instance of 50V) for the classical SCR is too high. As a result, there is a need for SCR-structures that trigger at intermediate voltages, or for which the trigger voltage can be adapted, depending on the application.
The present invention aims to fill this gap in protection devices. The present invention discloses a semiconductor device for electrostatic discharge or overvoltage protection applications, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages.
The present invention furthermore discloses a semiconductor device for electrostatic discharge or overvoltage protection applications, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages and said means being extendable with a third trigger component and possibly further trigger components, the addition of said third and further trigger components extending sequentially the range of the intermediate trigger voltages such that the protection trigger voltage can be adapted depending on the application.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, a semiconductor device for electrostatic discharge or overvoltage protection applications is disclosed, said device comprising means for absorbing an electrostatic discharge pulse or an overvoltage level, said means being triggered at intermediate voltages and said means including a series configuration of at least two trigger components. Said means can further be extended with a third trigger component and possibly further trigger components in said series configuration, the addition of said third and further trigger components extending sequentially the range of the intermediate trigger voltages. Said trigger components can comprise components, preferably diodes, with a specific breakdown voltage, the sum of the breakdown voltages of said diodes defining the specific intermediate trigger voltage of said device.
In another embodiment of the device of the invention according to the first aspect, the device can further comprise an integrated circuit having a functionality and an impedance being in the connection of said means to said circuit. The impedance can be replaced by any means being adapted for building up a voltage drop. The impedance preferably is a resistor. Said circuit further comprises components or has components in parallel or connected to the circuit, components that convert an overvoltage level or an electrostatic discharge pulse of an intermediate level into an electrical current, said current creating a voltage of an intermediate level over said impedance, said voltage triggering said means such that said overvoltage level or electrostatic discharge pulse is absorbed.
For the purpose of this patent application, the following terms are introduced here. A trigger component, or triggering component, has the meaning that in the devices of the invention, at least one component or the triggering component is made such that as a result of electrostatic discharge (ESD) pulses, current transients or overvoltage levels, this component is triggered thereby ensuring the clamping of the ESD-pulses, and snapback of the device to very low holding voltages. Thus, the electrostatic discharge pulses, current transients or overvoltage levels are absorbed in the device of the invention by making use of the above-introduced trigger components and further in such a way that a low power dissipation occurs in the device after tr
Groeseneken Guido
Russ Christian
Interuniversitair Microelektronia Centrum (IMEC)
McDonnell & Boehnen Hulbert & Berghoff
Ng{haeck over (o)} Ng{haeck over (a)}n V.
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