Device address locking to facilitate optimum usage of the...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation

Reexamination Certificate

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C710S020000, C710S021000, C710S037000

Reexamination Certificate

active

07383364

ABSTRACT:
A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.

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patent: 7069365 (2006-06-01), Zatorski
patent: 7134040 (2006-11-01), Ayres
Stephen D. Burd; System Architecture; 1998; Course Technology; 2nd Edition; pp. 73-78.

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