Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-21
2006-11-21
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07139985
ABSTRACT:
Embodiments of the invention include a system for an integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of a set of objects and hence the overall function. These objects are hierarchically composed from a set of primitive objects. By using a piece of hardware that can model any primitive object set as pre-established encapsulated hardware objects, the topology and properties define a piece of hardware that can perform the desired, implemented, functions. Using embodiments of the invention, circuit designers can design hardware systems with little or no knowledge of hardware or hardware design, requiring only a high-level software description.
REFERENCES:
patent: 5745124 (1998-04-01), Parks et al.
patent: 5778059 (1998-07-01), Loghmani et al.
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5907692 (1999-05-01), Wise et al.
patent: 6025853 (2000-02-01), Baldwin
patent: 6044211 (2000-03-01), Jain
patent: 6075935 (2000-06-01), Ussery et al.
patent: 6092174 (2000-07-01), Roussakov
patent: 6105083 (2000-08-01), Kurtze et al.
patent: 6112017 (2000-08-01), Wise
patent: 6112304 (2000-08-01), Clawson
patent: 6145073 (2000-11-01), Cismas
patent: 6150807 (2000-11-01), Osann, Jr.
patent: 6230307 (2001-05-01), Davis et al.
patent: 6233540 (2001-05-01), Schaumont et al.
patent: 6263422 (2001-07-01), Wise et al.
patent: 6289488 (2001-09-01), Dave et al.
patent: 6292925 (2001-09-01), Dellinger et al.
patent: 6298472 (2001-10-01), Phillips et al.
patent: 6308229 (2001-10-01), Masteller
patent: 6330659 (2001-12-01), Poff et al.
patent: 6353841 (2002-03-01), Marshall et al.
patent: 6370681 (2002-04-01), Dellarocas et al.
patent: 6435737 (2002-08-01), Wise et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6473769 (2002-10-01), Andrew et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6477697 (2002-11-01), Killian et al.
patent: 6483343 (2002-11-01), Faith et al.
patent: 6484304 (2002-11-01), Ussery et al.
patent: 6507947 (2003-01-01), Schreiber et al.
patent: 6553395 (2003-04-01), Marshall et al.
patent: 6597664 (2003-07-01), Mithal et al.
patent: 6606588 (2003-08-01), Schaumont et al.
patent: 6622233 (2003-09-01), Gilson
patent: 6633181 (2003-10-01), Rupp
patent: 6653859 (2003-11-01), Sihlbom et al.
patent: 6654889 (2003-11-01), Trimberger
patent: 6701515 (2004-03-01), Wilson et al.
patent: 6763327 (2004-07-01), Songer et al.
patent: 6765407 (2004-07-01), Snyder
patent: 6769056 (2004-07-01), Barry et al.
patent: 6775766 (2004-08-01), Revilla et al.
patent: 6795909 (2004-09-01), Barry et al.
patent: 6816562 (2004-11-01), Atkinson et al.
patent: 6826674 (2004-11-01), Sato
patent: 6836839 (2004-12-01), Master et al.
patent: 6847686 (2005-01-01), Morad et al.
patent: 6857110 (2005-02-01), Rupp et al.
patent: 6877150 (2005-04-01), Miller et al.
patent: 6889310 (2005-05-01), Cismas
patent: 2001/0025363 (2001-09-01), Ussery et al.
patent: 2002/0016918 (2002-02-01), Tucker et al.
patent: 2002/0100030 (2002-07-01), Souloglou et al.
patent: 2002/0124012 (2002-09-01), Liem et al.
patent: 2002/0126621 (2002-09-01), Johnson et al.
patent: 2002/0128037 (2002-09-01), Schmidt
patent: 2002/0129340 (2002-09-01), Tuttle
patent: 2002/0138716 (2002-09-01), Master et al.
patent: 2002/0181559 (2002-12-01), Heidari-Bateni et al.
patent: 2003/0054774 (2003-03-01), Plunkett et al.
patent: 2003/0056084 (2003-03-01), Holgate et al.
patent: 2003/0208723 (2003-11-01), Killian et al.
patent: 2003/0229482 (2003-12-01), Cook et al.
patent: 2004/0001296 (2004-01-01), Saito et al.
patent: 2004/0001445 (2004-01-01), Stansfield
patent: 2004/0068640 (2004-04-01), Jacobson et al.
patent: 2004/0078548 (2004-04-01), Claydon et al.
patent: 2004/0194048 (2004-09-01), Arnold
patent: 2004/0243984 (2004-12-01), Vorbach et al.
patent: 2005/0076187 (2005-04-01), Claydon
patent: 0772140 (1997-07-01), None
patent: WO99/39288 (1999-08-01), None
patent: WO02/080044 (2002-10-01), None
A. J. van der Hoeven, et al.,A Hardware Design System based on Object-Oriented Principles, 1991 IEEE Computer Society Press, pp. 459-463.
Eike Grimpe and Frank Oppenheimer,Object-Oriented High Level Synthesis Based on SystemC, 2001 IEEE, pp. 529-534.
T. Kuhn et al.,Object Oriented Hardware Synthesis and Verification, ISSS'01, Oct. 1-3, 2001, Montreal, Quebec, Canada.
Lu, et al., “Performance Analysis and Efficient Implementation of Latency Insensitive Systems,” Technical Report TR-ECE03-06, Mar. 2003, XP002337839, School of Electrical & Computer Engineering, Purdue University, p. 1, second paragraph, section 5.
Chelcea, T., et al., “A low-latency FIFO for mixed-clock systems,” IEEE Comput Society, Apr. 27, 2000, pp. 119-126, XP010379677, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip, Era, p. 3, right column, third paragraph, sections 4 and 5.
Carloni, L.P. et al., “A methodology for correct-by-construction latency insensitive design,” Computer-Aided Design, 1999, Digest of Technical Papers, 1999 IEEE/ACM International Conference, San Jose, CA, USA 7-11, Nov. 1999, Piscataway, NJ, USA, IEEE, US Nov. 7, 1999, pp. 309-315, XP010363870, ISBN: 0-7803-5832-5, abstract Sections 2, 5 and 6, figure 5.
Ruibing, Lu, et al.: “Performance Optimization of Latency Insensitive Systems through Buffer Queue Sizing of Communication Channels,” IEEE/ACM International Conference on Computer Aided Design, ICCAD 2003. IEEE/ACM Digest of Technical Papers, San Jose, CA, Nov. 9-13, 2003, IEEE/ACM International Conference on Computer-Aided Design, New York, NY; ACM, US Nov. 9, 2003, pp. 227-231, XPO10677157, ISBN: 1-58113-762-1, left-hand column, paragraph 1-page 1, right-hand column, paragraph 2.
Casu, M.R., et al.: “Issues in Implementing Latency Insensitive Protocols,” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceeding Feb. 16-20, 2004, Piscataway, NJ, USA, IEEE, vol. 2, Feb. 16, 2004, pp. 1390-1391, XPO10684987, ISBN: 0-7695-2085-5, p. 1, left-hand column, line 1—page 1, right-hand column, line 3.
Chandranmenon, G.P., et al: “Reconsidering Fragmentation and Reassembly,” Proceedings of the 17thAnnual ACM Symposium on Principles of Distributed Computing PODC 1998, Puerto Vallarta, Mexico, Jun. 28-Jul. 2, 1998, ACM Sigact—Sigmond Symposium on Principles of Distributed Computing, New York, NY: ACM; US, Jun. 28, 1998, pp. 21-29, XP002921718 ISBN: 0-89791-877-7; abstract, lines 1-6.
Jacobson, Hans M., et al., “Synchronous Interlocked Pipelines,” Proc. Eighth International Symposium on Asynchronous Circuits and Systems, (ASYNC'02) IEEE, 2002, pp. 1-10.
Ambric, Inc.
Lin Sun James
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