Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-10-02
2001-06-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06243853
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of in-circuit testing of printed circuit boards, and more particularly to a method and an apparatus for developing digital libraries used in creating executable tests for testing devices at the board level.
BACKGROUND OF THE INVENTION
In-circuit testing of printed circuit boards is a technology at least 25 years old. In-circuit tests look for manufacturing faults, as opposed to defects of the integrated circuits, that may occur during the assembly of the board. The in-circuit test presumes that the integrated circuits, or devices, are good as a result of earlier device testing and focuses on the quality of the manufacturing process by testing each device to ensure that it is placed and soldered correctly. As a by-product of this testing, the device logic is tested by checking input/output receivers and drivers for possible damage that may have occurred while the devices and board were handled during the manufacturing process.
In the simplest case of testing devices, a standalone device is tested by surrounding it with probes and applying digital inputs in order to observe digital outputs. If two or more devices are attached together, the in-circuit test will require probe contact with each node (i.e., where two or more pins converge). Each device is tested by stimulating all inputs and causing all outputs to change at least once. The goal is that if there is a failure at any input, that failure will propagate through the device so that an output will eventually respond incorrectly. The data used to test an individual device is referred to as predefined tests which can be used by an in-circuit tester.
Pre-defined tests are often not comprehensive enough to account for the different topological constraints that might occur on a complex circuit board. For example, where two devices are being tested and the output on a first device shares the same node as an input on a second device, testing the second device would entail overdriving competing outputs from the first, or upstream, device. While in-circuit testers have sufficient overdrive capability to win when establishing input states, it is possible for the upstream device to suffer damage due to this overdrive on its outputs. If this is a concern, the Pre-defined test may need to be augmented to condition the outputs of the upstream device such that damage is avoided. Similarly, a pre-defined test may need to be augmented where two devices have one of their output pins tied together so that if the first device is tested, the output on its pin may not be readable if the second device's output pin is enabled. As another example, a device can have an input tied directly to a fixed voltage such that the pin cannot be stimulated with data. This could rule out a pre-defined test for this device that was created with the assumption that the pin was free to move. A tied pin constraint can also occur where a device has two input pins tied to the same node. If a pre-defined test for such a device required different states to be applied to the pins at any one time, then the constraint would not allow the test to be applied.
In-circuit testers have dealt with these problems for many years. One solution has been to include an in-circuit program generator (hereinafter referred to as an IPG) in the test system that analyzes board interconnect topology and then attempts to build executable tests from an externally supplied digital library of pre-defined information and tests. These libraries are called digital libraries, and are manually created by engineers. The tests can either be written at the board level such that they are tailored to the device configuration on the board, or the tests can be written without knowledge of board configuration such that they anticipate different configurations of the board. This process of manually creating tests, however, is time-consuming, resource-consuming, and very expensive. Talented engineers may spend weeks analyzing a device, writing the tests, and then verifying them. As a result, the tests are often incomplete or of marginal quality. For example, disable methods for a device may be missing for some outputs, or the device may only have a presence and orientation test available. Additionally, if the tests are written at the board level, they are often written for a device configuration that is subsequently modified. As a result, the tests become outdated and need to be redesigned. Another solution is to use a library creation service provider to create digital library tests. However, these providers often only accept orders for widely used devices so that they can spread the cost over many users. As a result, service providers cannot handle the increasingly growing number of custom, one-of-a-kind devices.
While digital library tests can provide an IPG with the information necessary to create executable tests that consider the topological constraints of the board, they are time and labor intensive, expensive, and have the potential to be outdated very quickly. As a result, there is a need for a method and an apparatus of developing digital libraries to:
reduce the time and expense of creating device tests;
maximize the amount of information and tests that can be provided about a device;
increase the accuracy and reliability of device information; and
increase the probability that useful tests survive board level constraints.
SUMMARY OF THE INVENTION
The present invention addresses this need through automated digital library development. An automated digital library is a library of pre-defined information and tests for a device that is automatically extracted during device synthesis. Automated digital library development, therefore, is the recordation of predefined device information during device synthesis, which information is made available for in-circuit test application at the board level. Since device information and tests are predefined in a digital library, automated digital library development can automate the process of creating the digital library, thereby reducing the time and expense of manually creating it. As a result, more device information and tests can be generated. Additionally, since the information is recorded at the time the device is synthesized, the accuracy and reliability of the information is maximized. Automated digital library development, therefore, can provide comprehensive, accurate, and high quality information and tests for in-circuit test application at the board level.
Device information can include device pin, pin family, disable, and conditioning information. Device tests can include truth-table vectors for presence and orientation, pin wiggle, and logic verification tests. In automated digital library development, a basic, minimum library should comprise device pin information and pin family information. A more fully developed library can comprise pin disable and pin conditioning methods, as well as device tests. A complete, high quality automated digital library may include a presence and orientation test, pin wiggle test, and logic verification test.
In a preferred embodiment of the invention, an automated digital library is generated and made available for each device on a printed circuit board, and each digital library is used by a Hewlett-Packard HP-3070® in-circuit tester where an IPG analyzes board interconnect topology and then attempts to build executable tests for each device on the board from an automated digital library of information and tests.
These and other important advantages and objectives of the present invention will be further explained in, or will become apparent from, the accompanying description, drawings, and claims.
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patent: 5590136 (1996-12-01), Firooz
Nummela et al., “Strategies for Implementation Independent DSP System Development Using HDL Based Design Automation,” Proc. 5thAnnual IEEE Int'l ASIC Conference & Exhibit, pp. 214
Agilent Technologie,s Inc.
Garbowski Leigh Marie
Smith Matthew
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