Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-15
2007-05-15
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10965850
ABSTRACT:
A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to gerate a netlist, and expanding a hierarchy of the design, being the top hierarchy.
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Koga et al., “Mega Gate ASIC No Implement Sekkei”, Institute of Electronics, Information and Communication Engineers Gijutsu Kenkyu Kokoku, Institute of Electronics, Information and Communication Engineers, Sep. 22, 1998, vol. 98, No. 287, pp. 71-77.
Koga Chiaki
Nakayama Akitsugu
Tsuda Masayuki
Dinh Paul
Fujitsu Limited
Staas & Halsey , LLP
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