Deterministic generation of an integrated circuit...

Details Deterministic generation of an integrated circuit... Deterministic generation of an integrated circuit...

2005-09-23

2009-10-27

Chu, Chris C (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23179, C257S620000, C257S734000, C257S786000

Reexamination Certificate

active

07608932

ABSTRACT:
The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.

REFERENCES:
patent: 5262258 (1993-11-01), Yanagisawa
patent: 5477062 (1995-12-01), Natsume
patent: 6365443 (2002-04-01), Hagiwara et al.
patent: 6548827 (2003-04-01), Irie
patent: 6791197 (2004-09-01), Katz
patent: 7112889 (2006-09-01), Maruyama et al.
patent: 2003/0049871 (2003-03-01), Higashi

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