Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1998-10-30
2002-01-01
Luu, Le Hien (Department: 2152)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S058000, C710S005000, C710S007000
Reexamination Certificate
active
06336157
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the deterministic and ordered shutdown of interface controllers within communications network ports, and, in particular, to a method and system for a deterministic and ordered host processor-initiated shutdown of an interface controller and a deterministic and ordered interface controller-initiated shutdown upon detection of error conditions.
BACKGROUND OF THE INVENTION
The fibre channel (“FC”) is an architecture and protocol for a data communications network for interconnecting a number of different combinations of computers and peripheral devices. The FC supports a variety of upper-level protocols, including the small computer systems interface (“SCSI”) protocol. A computer or peripheral device is linked to the network through an FC port and copper wires or optical fibres. An FC port includes a transceiver and an interface controller, and the computer peripheral device in which the FC port is contained is called a “host.” The FC port exchanges data with the host via a local data bus, such as a peripheral computer interface (“PCI”) bus. The interface controller conducts lower-level protocol exchanges between the fibre channel and the computer or peripheral device in which the FC port resides.
An interface controller within an FC port serves essentially as a transducer between the serial receiver and transmitter components of the FC port and the host processor of the FC node in which the FC port is contained. The interface controller is concerned with, on the input side, assembling serially-encoded data received from the receiver component into ordered sets of bytes, assembling a majority of the ordered sets of bytes into FC frames, and passing the FC frames, along with status information, to the host processor within the context of larger collections of FC frames, called FC sequences and FC exchanges. On the output side, the interface controller accepts host memory buffer references and control information from the host processor and transforms them into FC frames within a context of FC sequences and FC exchanges, providing the FC frames to the transmitter component of the FC port for serial transmission to the FC. The interface controller communicates with the host processor through a set of host memory-based data structures and through a number of control registers accessible to both the interface controller and the host processor via a local bus, such as a PCI bus. At any given instant, the interface controller may be handling outgoing FC frames associated with different FC sequences, and may be also handling inbound FC frames from the FC associated with a number of FC sequences. The interface controller uses internal caches to cache information from the host memory-based data structures with which the interface controller communicates with the host processor. The interface controller plays an analogous function within an FC port as that played by a computer processor in a multi-tasking operating system environment. The interface control handles many different events concurrently with extremely dynamic patterns of state changes and information flow.
There are cases in which it is desirable, from the standpoint of the host processor, to stall or shutdown operation of the interface controller for a period of time. This is desirable for a number of reasons. For example, the host processor may wish to modify, reorder, or delete FC frames queued for transmission. The host processor may, in addition, need to substitute one data structure for another, or modify, reorder, or delete information contained within the data structures by which the host processor communicates with the interface controller. These host processor operations may be necessary for error processing, for implementing user-initiated abort requests, or for achieving priority-based transmission of FC frames. Because the internal state of the interface controller is complex and extremely dynamic, it is desirable to stall or shut down operation of the interface controller in a deterministic and ordered manner, so that operation of the interface controller can later be restored without undue interruption of ongoing transactions, lost and unaccounted for FC frames, and interruption of the network activities of other FC nodes interconnected by the FC.
Another case where interface controller shutdown may be required is when the interface controller detects certain error conditions, such as loss of connection to the FC. As with the host processor-initiated shutdown, shutdown of interface controller upon detection of error conditions should be accomplished in a deterministic and ordered manner.
Currently-available and previously-available interface controllers employ different methods for shutdown. In many interface controllers, shutdown results in a complete reset of the interface controller. This rather catastrophic method of shutdown may result in serious disruption of transactions that are in progress at the time of reset, may cause disruption to other FC nodes interconnected by the FC, and provide scant basis for the host processor to carry out any kind of recovery of interrupted transactions due to loss of context within the interface controller upon reset. In some interface controllers, a host processor depends upon receiving completion messages from the interface controller in order to monitor the activity of the interface controller to decide when to halt the interface controller. However, this method may still result in severe unanticipated disruption of ongoing transactions and may result in slow recovery times. Certain interface controllers include embedded processors that run error recovery firmware. This is, however, an expensive solution that can lead to performance problems. Finally, error recovery may be built into the hardware implementation of the interface controller, but this solution lacks flexibility. Error recovery methodologies may change as standards and markets evolve, and different types of applications may required different types of error handling, difficult or impossible to achieve in statically-defined hardware-implemented error recovery solutions.
A need has therefore been recognized by interface controller designers and manufacturers for a deterministic, non-destructive method for stalling, or shutting down, operation of interface controllers either by the host processor or by the interface controller in response to detection of error conditions by the interface controller. The desired method should make all shared data structures available to the host processor both for reading and for modification. Shutdown under the desired method is analogous to the shutdown of a computer processor within a multi-tasking operating system environment. Ongoing activities need to proceed to safe points at which they can be halted and sufficient information needs to be available for restart of the activities at a later time. It is desirable that this method not involve high-cost imbedded processors or low-flexibility, purely hardware solutions.
SUMMARY OF THE INVENTION
The present invention provides a network communications interface controller, operation of which can be deterministically stalled or halted by a host processor. In addition, the interface controller may deterministically stall or shutdown its own operation as a result of the detection of error conditions. The interface controller provides control registers by which a host processor can halt operation of the interface controller and restart operation of the interface controller. During shutdown, the interface controller stops receiving and sending data to the communications network, stops accepting tasks from the host processor, completes tasks for which control information has been cached in the interface controller, and notifies the host processor when the interface controller has reached a quiescent and non-operational state. Shared data structures and control registers through which the interface controller communicates with the host processor are then under complete control of the host p
Carbonaro Catherine H
Steinmetz Joseph H
Wakeley Matthew P
Agilent Technologie,s Inc.
Luu Le Hien
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