Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1996-04-08
1999-04-06
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711124, 711150, 711163, 711151, G06F 1200
Patent
active
058931600
ABSTRACT:
An efficient streamlined coherent protocol for a multi-processor multi-cache computing system. Each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, each global interface includes a request agent (RA), a directory agent (DA) and a slave agent (SA). The RA provides a subsystem with a mechanism for sending read and write request to the DA of another subsystem. The DA is responsible for accessing and updating its home directory. The SA is responsible for responding to requests from the DA of another subsystem. Each subsystem also includes a blocker coupled to a DA and associated with a home directory. All requests for a cache line are screened by the blocker associated with each home directory. Blockers are responsible for blocking new request(s) for a cache line until an outstanding request for that cache line has been serviced. A "locked" state managed by the blocker greatly reduces corner cases and simplifies solutions in the few remaining corner cases.
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Hagersten Erik
Loewenstein Paul N.
Kivlin B. Noel
Sun Microsystems Inc.
Swann Tod R.
Tzeng Fred F.
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