Deterministic collision detection

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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Reexamination Certificate

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07962698

ABSTRACT:
An embodiment of the present invention is directed to a method of deterministic collision detection involving at least two ports. The method includes receiving a read/write operation at a first data rate at a first port of a multi-port device, receiving a read/write operation at a second data rate at a second port of the multi-port device, detecting a collision between the first port and the second port if a same address space is accessed by the first port and the second port coincidentally, asserting a busy signal at least one of said first port and said second port a number of clock cycles after detecting said collision, storing an address location of said address space in a memory register, and deterministically report the collision using the address location and the number of clock cycles.

REFERENCES:
patent: 3931613 (1976-01-01), Gruner et al.
patent: 4393482 (1983-07-01), Yamada
patent: 4445172 (1984-04-01), Peters et al.
patent: 4493033 (1985-01-01), Ziegler et al.
patent: 4677594 (1987-06-01), Bisotto et al.
patent: 4755936 (1988-07-01), Stewart et al.
patent: 4901228 (1990-02-01), Kodama
patent: 4933909 (1990-06-01), Cushing et al.
patent: 4967398 (1990-10-01), Jamoua et al.
patent: 5187783 (1993-02-01), Mansfield et al.
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5224214 (1993-06-01), Rosich
patent: 5257236 (1993-10-01), Sharp
patent: 5261064 (1993-11-01), Wyland
patent: 5289427 (1994-02-01), Nicholes et al.
patent: 5293623 (1994-03-01), Froniewski et al.
patent: 5329630 (1994-07-01), Baldwin
patent: 5367650 (1994-11-01), Sharangpani et al.
patent: 5398211 (1995-03-01), Willenz et al.
patent: 5424995 (1995-06-01), Miyazaki et al.
patent: 5459851 (1995-10-01), Nakajima et al.
patent: 5469544 (1995-11-01), Aatresh et al.
patent: 5497470 (1996-03-01), Liencres
patent: 5502683 (1996-03-01), Marchioro
patent: 5526316 (1996-06-01), Lin
patent: 5530842 (1996-06-01), Abraham et al.
patent: 5534796 (1996-07-01), Edwards
patent: 5557768 (1996-09-01), Braceras et al.
patent: 5566124 (1996-10-01), Fudeyasu et al.
patent: 5661692 (1997-08-01), Pinkham et al.
patent: 5668967 (1997-09-01), Olson et al.
patent: 5673415 (1997-09-01), Nguyen et al.
patent: 5680542 (1997-10-01), Mulchandani et al.
patent: 5748968 (1998-05-01), Nally et al.
patent: 5752260 (1998-05-01), Liu
patent: 5752270 (1998-05-01), Wada
patent: 5768211 (1998-06-01), Jones et al.
patent: 5781480 (1998-07-01), Nogle et al.
patent: 5787489 (1998-07-01), Pawlowski
patent: 5875346 (1999-02-01), Luick
patent: 5956748 (1999-09-01), New
patent: 5999317 (1999-12-01), Sartore et al.
patent: 6021480 (2000-02-01), Pettey
patent: 6065107 (2000-05-01), Luick
patent: 6087527 (2000-07-01), Roth et al.
patent: 6094532 (2000-07-01), Acton et al.
patent: 6125421 (2000-09-01), Roy
patent: 6167487 (2000-12-01), Camacho et al.
patent: 6181595 (2001-01-01), Hawkins et al.
patent: 6256256 (2001-07-01), Rao
patent: 6345335 (2002-02-01), Flynn
patent: 6360307 (2002-03-01), Raftery et al.
patent: 6388939 (2002-05-01), Manapat et al.
patent: 6532524 (2003-03-01), Fan et al.
patent: 6545935 (2003-04-01), Hsu et al.
patent: 6598178 (2003-07-01), Yee et al.
patent: 6717834 (2004-04-01), Zagorianakos et al.
patent: 7120761 (2006-10-01), Matsuzaki et al.
patent: 7178000 (2007-02-01), Dobecki
patent: 7363436 (2008-04-01), Yeh et al.
patent: 7421559 (2008-09-01), Yadav
patent: 2007/0011388 (2007-01-01), Choi
U.S. Appl. No. 11/523,419: “Collision Detection Mechanism for High-Speed DDR,” Yadav et al.; 34 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/523,419 dated Apr. 3, 2009; 7 pages.
U.S. Appl. No. 11/015,959: “Apparatus and Method for a Synchronous Multi-Port Memory,” Yadav; 44 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/015,959 dated Feb. 7, 2007; 22 pages.
USPTO Final Rejection for U.S. Appl. No. 11/015,959 dated Aug. 10, 2007; 24 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/015,959 dated Sep. 25, 2007; 16 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/015,959 dated May 1, 2008; 8 pages.
Endo et al; “Pipelined, Time-Sharing Access Technique for an Integrated Multiport Memory,” IEEE Journal of Solid-State State Circuits, vol. 26, No. 4, Apr. 1991; 6 pages.
U.S. Appl. No. 09/633,514: “Dual Port SRAM,” Manapat et al.; 40 pages.
U.S. Appl. No. 09/538,822: “Port Prioritization Scheme,” Fan et al.; 22 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/688,904 dated Jul. 8, 1997; 3 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 08/688,904 dated Feb. 6, 1997; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/099,915 dated May 21, 2001; 4 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/099,915 dated Nov. 9, 2000; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/099,915 dated Mar. 16, 2000, 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/633,514 dated Aug. 30, 2001; 2 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/633,514 dated Mar. 29, 2001; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/538,822 dated Oct. 18, 2002; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 09/538,822 dated Aug. 22, 2002; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/538,822 dated Mar. 28, 2002; 6 pages.
Alves et al., “Built-In Self-Test for Multi-port RAMs” Written in 1991, IEEE. pp. 248-251; 4 pages.
Crawford et al., “Cache Coherence in a Multiport Memory Environment,” Written in 1994, IEEE, pp. 632-642; 11 pages.
“16K × 8/9 Dual-Port Static RAM with Sem, Int, Busy,” Cypress Semiconductor Data Book, May 1995, CY7C006 and CY7C016, pp. 6:1-17; 10 pages.
“4K × 16/18 and 8K × 16/18 Dual-Port Static RAM with Sem, Int, Busy,” Cypress Semiconductor Data Book, May 1995, CY7CO24/0241 and CY7CO25/0251, pp. 6:18-36; 11 pages.
“1K × 8 Dual-Port Static RAM,” Cypress Semiconductor Data Book, May 1995, CY7C130/CY7C131 and CY7C140/CY7C141, pp. 6:37-49; 8 pages.
“2K × 8 Dual-Port Static RAM,” Cypress Semiconductor Data Book, May 1995, CY7C132/CY7C136 and CY7C1421/CY7C146, pp. 6:50-62; 8 pages.
“2K × 16 Dual-Port Static RAM,” Cypress Semiconductor Data Book, May 1995, CY7C133 and CY7C143, pp. 6:63-73; 7 pages.
“4K × 8 Dual-Port Static RAM and 4K × 8 Dual-Port Static Ram with Semaphores,” Cypress Semiconductor Data Book, May 1995, CY7B134 and CY7B135 and CY7B1342, pp. 6:74-86; 8 pages.
“4K × 8/9 Dual-Port Static RAM with Sem, Int, Busy,” Cypress Semiconductor Data Book, May 1995, CY7B138 and CY7B139, pp. 6:87-102; 10 pages.
“8K × 8/9 Dual-Port Static RAM with Sem, Int, Busy,” Cypress Semiconductor Data Book, May 1995, CY7B144 and CY7B145, pp. 6:103-120; 11 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/523,419 dated Aug. 17, 2009; 7 pages.

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