Deterministic arbitration of a serial bus using arbitration...

Details Deterministic arbitration of a serial bus using arbitration... Deterministic arbitration of a serial bus using arbitration...

1998-10-21

2001-01-16

Ray, Gopal C. (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C710S120000

Reexamination Certificate

active

06175887

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computing systems, and more particularly to an apparatus, system, and method for deterministically arbitrating for a serial bus, preferably in an I
2
C environment.
2. Description of the Related Art
Serial communications are primarily differentiated from parallel communications by the transmission of data at the rate of one bit at a time. Serial communications are also simpler to implement since only a single data channel, either a single data line or a single differential pair, is needed. In recent years, serial communications have been increasingly popular with the introduction of such technologies and protocols as EEE 1394, the universal serial bus (USB), and the Inter IC (integrated circuit) bus, or I
2
C.
While 1394 and USB are primarily aimed at the computer system level, I
2
C was designed for serial communications between integrated circuits. Examples of such integrated circuits include single-chip microcontrollers, LCD drivers, random access memories (RAM), digital signal processors (DSPs), tuners, and DTMF generators. It is noted that the I
2
C protocol is also implemented by the ACCESS.bus for connecting peripherals to a computer.
Other than for power, only two lines are needed for an I
2
C-compatible bus, a serial data line (SDA) and a serial clock line (SCL). Each device is addressable by a unique address that may be set by software. The bus is controlled by a master device addressing a slave device, where the master device issues clock pulses on the serial clock line while transmitting data bits on the serial data line. The data line and the clock line are passively pulled HIGH except when a device actively asserts a LOW logic signal on the data line or clock line. A data bit is valid on the data line when the data bit is stable when the clock line is clocked HIGH. The I
2
C protocol only allows for data changes while the clock line is LOW.
Turning to
FIG. 1
, a typical I
2
C-compliant system
100
is shown. A plurality of master devices
110
A-
110
C and a plurality of slave devices
120
A-
120
C are each coupled to the serial data line
130
and the serial clock line
140
. It is noted that the total number of master devices
100
, also referred to as master-transmitters, and slave devices
210
, also referred to as slave-receivers, may be varied as desired up to the I
2
C capacitance limit for the serial bus of 400 pF. Master devices such as the first master device
110
A are unable to also act as slaves, while master devices such as the second master device
110
B, using what are termed master-receivers
112
, are also capable of acting as slave devices. Master device
110
B is shown including master-receiver
112
and control logic
113
for controlling access to the serial bus through bus interface logic
111
.
Devices coupled to a serial bus, such as the I
2
C-compatible bus, often each have a unique address associated with the device.
FIG. 2
illustrates the complete set of addresses
200
for devices connected to an I
2
C-compatible serial bus. Addresses are transmitted on the data line
130
as 8-bit bytes. The first seven bits are an actual device address and the eighth bit is the read/write bit, a “1” for a READ cycle and a “0” for a WRITE cycle. Using the 7-bit default addressing scheme, 128 device addresses are theoretically available in the complete set of addresses
200
. Sixteen of these addresses are reserved
205
. In any given implementation, some number of addresses will be in use (assigned to devices connected to the bus)
210
and the remainder of the addresses will be available
220
.
It is noted that in the I
2
C protocol, master devices
110
are assigned addresses in at least two cases. First, when the master device
110
C issues “hardware general calls”. This situation applies to “dumb” master devices
110
C that do not know the address of the slave device
120
to which they wish to transmit data. The dumb master device
110
C thus issues a hardware general call in a first byte and its own address in the second byte. The second case is where the master device
110
B includes a master-receiver
112
, or is otherwise capable of becoming a master-receiver.
Communication sequences
300
on the serial bus are detailed in
FIG. 3. A
master device
110
is only allowed, under the I
2
C protocol, to take control of the serial bus when the serial bus is free
299
, that is, when no data transmission traffic from another communication sequence
300
is taking place over the serial bus. A communications sequence
300
comprises, as a minimum, a START condition
310
, an initial address phase
320
, an initial data phase
330
, and a STOP condition
390
. The communications sequence
300
may optionally also include one or more repeated START conditions
315
, repeated address phases
325
, and repeated data phases
335
. Shown in a flowchart embodiment in
FIG. 3
, the communications sequence
300
of an I
2
C-compliant bus includes decision blocks
340
and
345
for continuing or ending the communications sequence
300
.
It is noted that the initial data phase
330
and the repeated data phases
335
may include the transfer of a data block comprising one or more bytes of data. A slave device receiving the data block typically acknowledges each byte of data in the data block, upon receipt. A master device receiving the data block typically acknowledges each byte of data in the data block, upon receipt, except for the final byte. This alerts the sending slave device that the data phase
330
/
335
is at an end.
The START condition
310
comprises a master device
110
transitioning the data line
130
from a logic HIGH to a logic LOW while the clock line
140
is at a logic HIGH. Similarly, the STOP condition
390
comprises the master device
110
transitioning the data line
130
from the logic LOW to the logic HIGH while the clock line is at the logic HIGH. Address and data bits from the address
320
/
325
and data
330
/
335
phases are transmitted on the data line
130
and held stable at either logic LOW or logic HIGH while the clock line
140
is clocked at logic HIGH. The logic HIGH or logic LOW of the data line
130
is only changed when the clock line
140
is at the logic LOW. It is noted that a logic LOW preferably represents a “0” and logic HIGH preferably represents a “1”.
It is noted that in the I
2
C environment, master devices
110
generate their own clock signals on the clock line
140
. All devices attached to the serial bus are connected to the clock line
140
in a wired-AND configuration. Once clocked LOW by a master device
110
, the wired-AND holds the clock line
140
in the LOW logic state until all devices communicating over the bus are ready for the next clock logic HIGH. One purpose of the wired-AND is to prevent a fast master
110
device from transmitting too quickly to a slow slave device
120
. The slave device
120
can stretch out the logic LOWs of the clock cycle on the clock line
140
until the slave device
120
is able to accept a next data bit on the data line
130
. If necessary, the master device
110
enters wait states until the slave device
120
releases the clock line
140
and the clock line transitions to the logic HIGH.
Arbitration for control of the bus in an I
2
C environment is such that, at any time during which the bus is free, any or all of the master devices
110
may start a new communications sequence
300
on the bus. The I
2
C arbitration scheme is completely non-deterministic. It is possible for two or more masters
110
to transfer the same data byte to the same slave device
120
in the same communications sequence
300
with no ill effects on the I
2
C system. In fact, all of the master devices
110
involved would continue as if they were the controlling master device
110
on the bus.
Whenever two or more master devices
110
X and
110
Y generate the START condition
310
on the data line
130
of the serial bus at the same time, each master device
110
X/
110
Y proceeds to convey the initial

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