Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1998-01-29
2000-10-17
Nguyen, Hiep T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711219, 710 50, 365221, G06F 1202
Patent
active
061346292
ABSTRACT:
Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than or equal to the write address. When the write address for the FIFO queue is less than the read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than the write address plus a maximum depth of the FIFO queue. A first read transaction of the first transaction size from the FIFO queue is performed only when the first condition flag is true.
REFERENCES:
patent: 4839866 (1989-06-01), Ward et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 5668767 (1997-09-01), Barringer
Hewlett--Packard Company
Nguyen Hiep T.
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