Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-11
2008-11-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07451423
ABSTRACT:
A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell instances of the configuration memory cell. An identification of the tile module is input. Characterization data is input for each configuration memory cell specifying address and data input pins. Characterization data is input for each configuration control module specifying a first ordered set of address output pins and a second ordered set of data output pins. For each of the cell instances, the first index of an address output pin in the first ordered set and the second index of a data output pin in the second ordered set are determined and a specification is output of the cell instance and the first and second indices.
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Barei James F.
Bean Keith R.
Kirkwood Daniel P.
Ralston Benjamin D.
Reynolds Bart
Chiang Jack
Doan Nghia M
Maunu LeRoy D.
Xilinx , Inc.
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