Determining feasibility of IC edits

Details Determining feasibility of IC edits Determining feasibility of IC edits

2006-10-03

2006-10-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07117476

ABSTRACT:
A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.

REFERENCES:
patent: 5392222 (1995-02-01), Noble
patent: 5675499 (1997-10-01), Lee et al.
patent: 6557162 (2003-04-01), Pierrat
patent: 2002/0166103 (2002-11-01), Rittman et al.
patent: 2005/0216877 (2005-09-01), Pack et al.

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