Determining an optimal sampling clock

Details Determining an optimal sampling clock Determining an optimal sampling clock

2007-07-17

2007-07-17

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000, C375S375000

Reexamination Certificate

active

10262601

ABSTRACT:
In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.

REFERENCES:
patent: 6118307 (2000-09-01), Shi et al.
patent: 6320921 (2001-11-01), Gu
patent: 6373911 (2002-04-01), Tajima et al.
patent: 6861886 (2005-03-01), Ludden et al.
patent: 2002/0085656 (2002-07-01), Lee et al.
patent: 10303875 (1998-11-01), None

Affiliated with

Also associated with

Rating

Determining an optimal sampling clock does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Determining an optimal sampling clock, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Determining an optimal sampling clock will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3766309