Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-01
2002-03-05
Everhart, Caridad (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S002000, C703S016000, C703S019000, C702S064000, C702S066000
Reexamination Certificate
active
06353917
ABSTRACT:
FIELD OF THE INVENTION
This application relates to integrated circuit (IC) design and, specifically, to interconnect coupling effects on delay analysis in high speed, high density IC design.
BACKGROUND OF THE INVENTION
In order to achieve high speed operations of high density ICs, special attention is paid to the method of interconnecting various components in the IC. For high speed signals, a wire and its environment becomes a relatively complex circuit element along which the signals propagate with finite speed. Hence, a wire, also known in the context of ICs as an interconnect, net or line, is an important IC performance limiting factor. Therefore, special care is taken as to the characteristics of interconnects, their routing and the performance limiting factors associated with interconnects.
For instance, signal energy reflection returned along an interconnect to the signal origin point may cause ringing or a “bumpy” rising edge. To maintain the integrity of signals propagating through interconnects, the geometry (e.g., length) of interconnects is controlled relative to the rise time of signals. Additionally, interconnects configured as transmission lines are typically terminated with a resistance corresponding to the characteristic impedance of such interconnects.
As a further example, signal crosstalk between coupled interconnects can cause false switching and may accentuate signal propagation delays. Crosstalk is typically attributed to the capacitive coupling of closely proximate (e.g., parallel) interconnects, and the extent of crosstalk is influenced by the switching speed of signals. Crosstalk is also influenced by the geometry (e.g., length) of interconnects and the density of interconnects routing.
In order to determine the impact of crosstalk on the signal propagation delay, conventional timing analysis tools assume a coupling capacitance that is equivalent to a grounded capacitance multiplied by a factor known as the switching factor which depends upon the switching conditions. A switching factor of zero (0) is used for signals that switch in the same direction at both aggressor and victim interconnects. A switching factor of not higher than two (2.0) is customarily used for signals that switch in the opposite direction at the aggressor and victim interconnects. For use in delay and noise estimation a determination of a single effective capacitance value is made which characterizes the interconnect. The resulting effective capacitance is then multiplied by the switching factor.
In some cases, assuming a switching factor of 2.0 underestimates the delay effects of crosstalk. However, conventional IC design consistently employs this assumption. Accordingly, there remains a need for optimizing the design of interconnecting various components in the IC. The present invention addresses this and related problems.
SUMMARY OF THE INVENTION
A preferred embodiment of the present invention provides a more accurate determination of switching factor values for coupled interconnects. The switching factor values reflect the effects of capacitive coupling between interconnects and are used to optimize the design of interconnecting IC components. The present invention provides that the switching factor is derived from a ratio of slew times of aggressor and victim interconnects voltages. The present invention further provides that under worst case capacitive coupling the switching factor may be 3.0 or more.
For example, in accordance with the present invention, the switching factor under worst case conditions is 3.0 for linear ramp voltages and more than 3.0 for voltages with exponential waveforms. With the more accurate estimation of switching factor values, the present invention provides a more accurate representation of worst case scenarios for optimizing the design of IC components interconnections. In contrast with conventional methods where switching factor values are limited to 2.0, the more accurate estimation of the switching factor values overcomes the common problem of underestimating switching factor values. Moreover, the more accurate estimation of switching factors more closely addresses timing problems in critical interconnect coupling cases.
The present invention also provides model circuits, configured as lumped &pgr; models, of the coupled interconnects for simpler and no less accurate switching factor and propagation delay analysis. The lumped &pgr; models of the interconnects replace the coupled RC network model of the coupled interconnects, and the total effective capacitance (coupling capacitance modified by the switching factor, e.g., 3C) replaces each coupling capacitance. In other words, the coupled RC network model of the coupled interconnects is de-coupled with the lumped &pgr; models, allowing individual analysis of each interconnect.
In accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method for determining a switching factor. The method includes applying a voltage to each interconnect of a pair of interconnects, each voltage having a waveform and a slew time. The method also includes dividing the voltage waveform into time regions, and analyzing a behavior in each of the time regions of a capacitor that represents capacitive coupling between the interconnects pair by determining a value of an effective capacitance as seen from one of the interconnects. The method further includes determining a total effective capacitance by time averaging the effective capacitance values, and determining the switching factor from the total effective capacitance.
The switching factor is a function of a ratio between the slew times, wherein a time-averaged effective value of the switching factor corresponds to the total effective capacitance. The time-averaged effective value of the switching factor is accounted for in optimizing a design of integrated circuit (IC) components interconnections. The value of the switching factor ranges between zero (0) and a maximum value, and it varies based on logic state switching conditions of the voltages including their respective waveforms and slew times, and their relative start times and directions of switching. The time-averaged effective value of the switching factor is three (3.0) for linear ramp voltage waveforms, and greater than three for non-linear voltage waveforms.
In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method of optimizing IC components interconnections design with switching factor analysis. The design optimizing method includes determining a switching factor for a pair of coupled interconnects under worst case conditions, the switching factor being a function of a ratio between slew rates of signals at the coupled interconnects. The method further includes modeling the pair of coupled interconnects using lumped &pgr; (Pi) models each having a total effective capacitance that is scaled by the switching factor, and performing a time delay analysis using the lumped &pgr; models. The effective capacitance represents a time-averaged coupling capacitance between the coupled interconnects. The switching factor is determined from the total effective capacitance.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.
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NN86112774, “Calculation of AC Power in CMOS Circu
Muddu Sudhakar
Sarto Egino
Everhart Caridad
Kik Phallaka
Silicon Graphics Inc.
Squire Sanders & Dempsey LLP
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