Determine output of a read/write port

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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Details

C365S189070, C365S189110, C365S203000

Reexamination Certificate

active

06317379

ABSTRACT:

TECHNICAL FIELD
The invention relates to computer memory devices. More particularly, the invention relates to electronic devices and methods for ensuring proper read outputs of a write/read port of a multi-port memory, e.g., a dual port RAM.
BACKGROUND ART
A modern computer system is typically equipped with multiple processors (albeit on a single chip) processing many instructions (or kernels) in parallel. Each of the multiple processors requires real time independent access to a common memory shared by the processors to store and retrieve instructions and/or data needed to process the instructions. In other words, the processors need simultaneous and independent access to the same shared memory device. To accomplish this functionality, a memory with multiple access ports can be used. Moreover, a multiple access port memory may be useful in any application in which simultaneous multiple access is required, e.g., pipelined cache applications.
There is, however, a limit on how many access ports can be provided in a single memory device. The limit is due to, e.g., inter alia, constraints in the ability provide many layers of metal runs during chip manufacturing, and the complexity of logic circuitry to arbitrate accesses of memory cells between the processors. Typically, the number of ports is limited to between two and four ports. These ports may be a combination of read and/or write ports.
For example, a conventional dual port random access memory (RAM)
100
shown in FIG.
1
. The RAM comprises a memory cell core
101
comprising an array of memory cells. The memory cells are typically arranged as a plurality of rows and columns, and are individually addressable using the corresponding row and column locations, e.g., ARRAY (row, column), as the indices for their address. The write port address decoder
104
and the read/write port address decoder
105
generate the row and column addresses from the write address
107
and the read/write address
110
input thereto, respectively.
The dual port RAM
100
includes a write port P
1
comprising the write data input
106
and the write address input
107
, and a read/write port P
2
comprising the read data output
112
, the write data input
111
and the read/write address input
110
. The write port P
1
and the read/write port P
2
each provide independent access to the memory core
101
by more than one entity. When an entity wishes to write to the write port, it must present the data to be written, the address of the cell to which the data is to be written, at the write data input
106
and the write address input
107
, respectively, as well as a control signal, e.g., inter alia, write enables, at the control signal input
108
. Likewise, when an entity wishes to write to the read/write port, it needs to present the data and the address of the cell at the write data input
111
and the read/write address input
110
, respectively, and a control signal at the control signal input
109
.
Additionally, the read/write port may be accessed to read data contained in one or more of the memory cells
101
. A dynamic read operation is performed when the address of the cell from which to read is provided at the read/write address input
110
. During a read operation, the content of the memory cell corresponding to the read address is output at the read data output
112
.
The control and address arbitration logic
102
provides the necessary control signals and arbitration of the access to the memory cell core
101
between the two ports, particularly when an access of the same memory cell is sought by both of the ports at the same time.
The precharge circuit
103
comprises a precharge and hold circuit for dynamically precharging the read outputs with the supply voltage level (V
DD
) during a read operation. The practice of precharging the outputs to implement dynamic read operations is well known to those familiar with memory designs.
FIG. 2
shows an example of a precharge and hold circuit
200
of a conventional memory, e.g., the dual port RAM
100
of FIG.
1
. The precharge and hold circuit
200
includes a transistor Q
1
205
which ensures that the precharging of the outputs (shown in the example as the port pad
210
representing a plurality of outputs of one or more banks of memory cells, e.g., a 64×1 bank comprising 64 cells) are precharged, i.e., dynamically pulled up to the supply voltage (V
DD
), only during a proper clock cycle, e.g., when the clock signal received from the clock input
201
is LOW. The transistors, Q
3
207
, Q
4
208
and Q
5
209
collectively regulate the holding of the charge during the next clock phase, e.g., while the clock is HIGH.
By bringing together the outputs of a plurality of memory cells, typically referred to as a bank, to the port pad
210
, a precharge and hold circuit
200
may be provided for each bank of cells rather than to each individual cell.
FIG. 3
shows an exemplary block diagram of the relevant portions of a single memory cell
300
, e.g., a cell from the bank of cells connected to the port pad
210
, and of which the precharge signal
304
corresponds to the voltage level of the port pad
210
. The logic level of the output
302
depends on the logic state contained in the cell logic
301
. For example, if the cell logic
301
contains therein a zero (0), then the output
302
is pulled down by the cell logic
301
to output a zero (0). If on the other hand the cell logic
301
contains a logic one (1), then the output
302
outputs the pulled up voltage, i.e., VDD, to output a logic one (1). Of course, the memory cell may be designed so that the output
302
may be an inverted output, i.e., when the cell logic
301
contains therein a zero (0),then the output
302
is pulled up to output a one (1).
Unfortunately, the conventional multi-port memories described above suffer from significant drawbacks. Unknown and unstable output voltage levels may be read from the read outputs of the read/write port during a write operation to the port, particularly during a multiple write operation (i.e., the same memory cell is being written into from more than one port). The unknown and unstable output voltage levels may cause a degradation of the integrity of the semiconductor device and/or the logic signals within the memory device. In particular, for example, in a conventional dual port RAM
100
described above, when a logic one (1) is being written to a cell from the write port, and a logic zero (0) is being written to the same cell from the read/write port substantially simultaneously, the output
302
may be partially switched, and may end up outputting a voltage level somewhere between V
DD
and GND. The in between voltage may be close to the threshold voltage for, and thus may cause oscillations of, other switches (or transistors) of the memory circuitry, and may therefore be detrimental to the integrity of the memory device.
Moreover, the arbitrary nature of the above conventional multi-port memories makes it difficult to test the memory device, e.g., for design and/or performance verification.
Attempts to alleviate the above problems heretofore have involved addition of elaborate arbitration and decoder circuitry to altogether disable the read operation during a write operation. However, the addition of the arbitration and decoder circuitry exacerbates the physical semiconductor space constraints discussed above, and adds delay. This delay may result in violation of designed timing allocation, and thus would require a redesign.
There is therefore a need for a more efficient and robust method and device for ensuring deterministic logic levels. There is a need for ensuring deterministic logic levels of the read outputs of a read/write port of a multi-port memory without a significant additional circuitry and design complexity.
SUMMARY OF INVENTION
A method and apparatus for providing deterministic read output valves for a multi-port memory are described. More specifically, a method of, and an apparatus for, providing a deterministic read output value of a multi-port memory having

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