Determination of parasitic capacitance between the gate and...

Details Determination of parasitic capacitance between the gate and... Determination of parasitic capacitance between the gate and...

1999-07-27

2001-01-02

Ngo, Ngan V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S048000, C257S300000, C257S401000

Utility Patent

active

06169302

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to field effect transistors such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and more particularly, to a device for determining the component of the parasitic capacitance between the gate and the drain or source local interconnect of a field effect transistor.
BACKGROUND OF THE INVENTION
Field effect transistors, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), are now widely used within integrated circuits. Referring to
FIG. 1
, a cross sectional view of a typical MOSFET
102
, as known to one of ordinary skill in the art, includes a drain region
104
and a source region
106
. A channel region
108
is disposed between the drain region
104
and the source region
106
. A gate dielectric
110
is disposed on the channel region
108
, and a conductive gate region
112
is disposed on the gate dielectric
110
. A drain local interconnect
114
is coupled to the drain region
104
for providing electrical connection to the drain region
104
, and a source local interconnect
116
is coupled to the source region
106
for providing electrical connection to the source region
104
. A dielectric region
118
surrounds the drain local interconnect
114
, the source local interconnect
116
, and the conductive gate region
112
.
Parasitic capacitance components are formed by these device regions of the MOSFET
102
. Referring to
FIG. 1
, a gate to drain parasitic capacitance component
120
is formed between the conductive gate region
112
and the drain region
104
of the MOSFET
102
. The gate to drain parasitic capacitance component
120
is formed predominantly from the overlap of the gate dielectric
110
over the drain region
104
and from the fringing electric field between the conductive gate region
112
and the drain region
104
, as known to one of ordinary skill in the art of electronics. Similarly, a gate to source parasitic capacitance component
122
is formed between the conductive gate region
112
and the source region
106
of the MOSFET
102
. The gate to source parasitic capacitance component
122
is formed predominantly from the overlap of the gate dielectric
110
over the source region
106
and from the fringing electric field between the conductive gate region
112
and the source region
106
, as known to one of ordinary skill in the art of electronics.
In addition, referring to
FIG. 1
, a gate to drain local interconnect parasitic capacitance component
130
is formed between the conductive gate region
112
and the drain local interconnect
114
. Similarly, a gate to source local interconnect parasitic capacitance component
132
is formed between the conductive gate region
112
and the source local interconnect
114
.
In the prior art, the gate to drain parasitic capacitance component
120
and the gate to source parasitic capacitance component
122
are typically accounted for in device analysis and device modeling in the design of the integrated circuit having the MOSFET
102
. However, the gate to drain local interconnect parasitic capacitance component
130
and the gate to source local interconnect parasitic capacitance component
132
are typically not included in such device analysis and device modeling in the design of the integrated circuit having the MOSFET
102
. However, as device dimensions are further scaled down, the gate to drain local interconnect parasitic capacitance component
130
and the gate to source local interconnect parasitic capacitance component
132
become more significant parasitic capacitance components.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET
102
are further scaled down to submicron and nanometer dimensions, the gate to drain local interconnect parasitic capacitance component
130
and the gate to source local interconnect parasitic capacitance component
132
become more significant parasitic capacitance components. Thus, such parasitic capacitance components need to be accounted for in device analysis and device modeling for an accurate design of the integrated circuit having the MOSFET
102
. As a result, a mechanism for determining the gate to drain local interconnect parasitic capacitance component
130
and the gate to source local interconnect parasitic capacitance component
132
of the MOSFET
102
is desired.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the present invention is to accurately determine a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and for determining a second parasitic capacitance component between the conductive gate region to a source local interconnect of the real field effect transistor.
Generally, with the present invention, a virtual field effect transistor is fabricated on a dielectric in order to determine the parasitic capacitance component between just the gate and the drain or source local interconnect of the real field effect transistor. The virtual field effect transistor of the present invention includes a virtual drain local interconnect fabricated on the dielectric. The virtual drain local interconnect has a size that is substantially equal to a size of the drain local interconnect of the real field effect transistor. In addition, the virtual field effect transistor of the present invention includes a virtual source local interconnect fabricated on the dielectric. The virtual source local interconnect has a size that is substantially equal to a size of the source local interconnect of the real field effect transistor. Also, the virtual field effect transistor of the present invention includes a virtual conductive gate region fabricated on the dielectric. The virtual conductive gate region has a size that is substantially equal to a size of the conductive gate region of the real field effect transistor.
The positions of the virtual drain local interconnect, the virtual source local interconnect, and the virtual conductive gate region, relative to each other on the dielectric, are substantially the same as positions of the drain local interconnect of the real field effect transistor, the source local interconnect of the real field effect transistor, and the conductive gate region of the real field effect transistor, relative to each other.
Furthermore, a virtual dielectric region is fabricated on the dielectric to surround the virtual drain local interconnect, the virtual source local interconnect, and the virtual conductive gate region. The virtual dielectric region is substantially the same as a dielectric region that surrounds the drain local interconnect of the real field effect transistor, the source local interconnect of the real field effect transistor, and the conductive gate region of the real field effect transistor.
The first parasitic capacitance component between the conductive gate region of the real field effect transistor to the drain local interconnect of the real field effect transistor is a first capacitance measured between the virtual conductive gate region and the virtual drain local interconnect. Similarly, the second parasitic capacitance component between the conductive gate region of the real field effect transistor to the source local interconnect of the real field effect transistor is a second capacitance measured between the virtual conductive gate region and the virtual source local interconnect.
The present invention may be used to particular advantage when the first parasitic capacitance component and the second parasitic capacitance component are used to determine a mismatch in a first distance, between th

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