Determination of cache entry for future operation

Details Determination of cache entry for future operation Determination of cache entry for future operation

2008-04-22

2008-04-22

Otto, Alan M (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S131000, C711S133000, C326S104000

Reexamination Certificate

active

07363430

ABSTRACT:
A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K layers M/2 decision cells of a first layer to indicate the other one of the respective two of the M cache entries and to transmit a hit signal in response to the signal, a second layer of M/4 decision cells to enable the other one of the respective two of the M/2 decision cells of the first layer and transmit a second hit signal in response to the signal, a (K−1)th layer of two decision cells to enable the other one of the respective two decision cells of the (K−2)th layer and transmit a third hit signal in response to the second hit signal, and a Kth layer of a root decision cell to enable the other one of the respective two decision cells of the (K−1)th layer in response to the third hit signal.

REFERENCES:
patent: 5274790 (1993-12-01), Suzuki
patent: 5367659 (1994-11-01), Iyengar et al.
patent: 5594886 (1997-01-01), Smith et al.
patent: 2003/0200404 (2003-10-01), Wicki et al.

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