Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1999-03-10
2002-01-29
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S005000, C710S010000, C713S300000, C713S500000, C713S600000, C713S601000
Reexamination Certificate
active
06343334
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a detector of an oscillation stopping for detecting an oscillation stopping of an external oscillator, which provides an external clock to a micro computer, and for generating a signal to reset the micro computer or for generating a signal to execute an interruption command, when such an oscillation stopping is detected. The present invention relates also to an apparatus for executing a treatment after the detection of an oscillation stopping.
2. Description of the Prior Art
FIG. 6
shows a block diagram of a detector of an oscillation stopping in the prior art. Reference numeral
1
denotes a oscillator,
2
is a micro computer formed on a semiconductor substrate (or a semiconductor chip). The micro computer
2
comprises the following elements
3
-
8
, which are provided on a semiconductor substrate. A clock signal generator
3
generates a clock signal, and is connected to the oscillator
1
. A CPU
4
, which functions according to the clock signal, generates a reset command periodically. A timer reset circuit
5
generates a reset pulse in response to the reset command. A pulse generating circuit
6
generates a pulse signal at a constant period. An eight bit timer
7
increments its count value in response to the pulse signal from the pulse generating circuit
6
and resets the count value in response to the reset pulse from the timer reset circuit
5
. The eight bit timer outputs an over flow signal, when the count value reaches to a predetermined value. A reset signal generating circuit
8
generates a reset signal for resetting the micro computer
2
, in response to the over flow signal from the eight bit timer
7
.
FIG. 3
shows a block diagram of a LAN system comprised of a plurality of micro computers. Reference numeral
9
is a serial bus, and a plurality of micro computers are connected to nodes
10
1
-
10
N
on the serial bus
9
.
The system functions as follows. When the micro computers have a communication function, they can transfer data to each other through the serial bus
9
. However, when an accident occurs, for example, the oscillator of a micro computer is disconnected, while the micro computer is transferring data, then the micro computer stops and continues to output a dominant level signal (for example “H” level signal) or a recessive level signal (for example “L” level signal) to the serial bus
9
.
When the micro computer stops and continues to output the “L” level signal onto the bus, the influence to the other micro computers are rather small, and they can communicate to each other through the serial bus
9
. On the other hand, when the micro computer stops and continues to output the “H” level signal, the other micro computers cannot communicates to each other. Because even if one of the other computers outputs an “L” level signal onto the serial bus
9
, the signal level in the serial bus
9
does not change to the “L” level. As a result, the communication is no longer possible.
When such an accident occurs, a reset of the micro computer is necessary, so as to cancel the state, in which the “H” level signal is outputted continuously to the serial bus
9
. After such an accident, the detector of an oscillation stopping in the prior art resets the microcomputer as follows.
In a normal state, namely no accident occurred, for example, no oscillator is disconnected, the CPU
4
functions in synchronization with the clock signal from the clock signal generating circuit
3
. And the CPU generates a reset command signal periodically. The timer reset circuit
5
generates a reset pulse in response to the reset command. The count value of the eight bit timer
7
is reset by this reset pulse periodically. Thus, no over flow signal is outputted from the eight bit timer
7
. As a result, the reset signal generating circuit
8
outputs no signal to reset the micro computer
2
.
On the other hand, when an accident occurs, for example, the oscillator
1
is disconnected, no clock signal is supplied to the CPU
4
from the clock generating circuit
3
, and the CPU
4
stops its function. Thus the CPU
4
does not generate the reset command. As result, the timer reset circuit
5
cannot generate the reset pulse to reset the eight bit timer
7
. Consequently, the eight bit timer
7
increases its count value according to the pulse from the pulse generating circuit
6
, until it overflows to output an over flow signal to the reset signal generating circuit
8
. When the reset signal generating circuit
8
receives the over flow signal from the eight bit timer
7
, it generates a reset signal to reset the micro computer
2
. Once the micro computer
2
is reset, the state outputting the “H” level signal to the serial bus
9
is cancelled.
The detector of an oscillation stopping in the prior art, constructed as aforementioned, can reset the micro computer
2
, when the micro computer
4
stops its function after the accident, for example, the disconnection of the oscillator
1
. However, while the CPU
4
functions normally the CPU
4
must always output the reset command periodically. Thus, the load of the CPU
4
is large.
Moreover, if the oscillator
1
stops, while the CPU
4
is outputting a reset command, the CPU
4
continues to output the reset command. Thus, the count value of the eight bit timer
7
does not overflow after the stopping of the oscillator
1
. As a result, the reset signal generating circuit
8
cannot generates the reset signal.
Further, the stopping of the oscillation
1
is detected by the over flow signal of the eight bit timer, however, it takes a long time until the eight bit timer overflows. As a result, it takes a long time until the stopping of the oscillation can be detected, and treatments of the micro computer
2
cannot be started promptly after the stopping of the oscillator
1
.
SUMMARY OF THE INVENTION
An object of the present invention is to propose a detector of an oscillation stopping, which can eliminate the aforementioned drawbacks.
Another object is to propose a detector of an oscillation stopping, which detects quickly the oscillation stopping of an external oscillator, without increasing the work of the CPU. Such detector shall generate a reset signal of the micro computer or an interruption signal to the CPU, in order to treat the CPU or the micro computer promptly after the stopping of the oscillation.
The detector of an oscillation stopping, according to the present invention, comprises a one shot pulse generating circuit, which generates a one shot pulse, when it detects an external clock signal, a charge/discharge circuit, which charges, while the one shot pulse is not generated, and discharges, while the one shot pulse is generated, and an interruption signal generating circuit, which generates an interruption signal for initializing the micro computer, when the charged voltage of the charge/discharge circuit exceeds a predetermined value.
An apparatus for executing a treatment after the detection of an oscillation stopping, as an embodiment of the present invention, comprises a one shot pulse generating circuit, which generates a one shot pulse, when it detects an external clock signal, a charge/discharge circuit, which charges, while the one shot pulse is not generated, and discharges, while the one shot pulse is generated, an oscillation stopping signal generating circuit, which generates an oscillation stopping signal, when the charged voltage of the charge/discharge circuit exceeds a predetermined value, an internal clock generating circuit, which is formed as a ring oscillator or as a CR oscillator and is actuated by the signal indicating that the oscillation is stopping, for supplying an internal clock signal to the micro computer, and an interruption signal generating circuit for generating and supplying an interruption signal to the CPU in response to the oscillation stopping signal.
A detector of an oscillation stopping or an apparatus for executing a treatment after the detection of an oscillation stopping, as an em
Cho Yoshiki
Uemura Toshiyuki
Burns Doane , Swecker, Mathis LLP
Lee Thomas
Mitsubishi Electric System LSI Design Corporation
Perveen Rehana
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