Detector circuit for testing semiconductor memory device

Details Detector circuit for testing semiconductor memory device Detector circuit for testing semiconductor memory device

1992-07-17

1995-03-21

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

365233, G11C 2900

Patent

active

054002826

ABSTRACT:
A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.

REFERENCES:
patent: 4751679 (1988-06-01), Dehganpour
patent: 4954994 (1990-09-01), Hashimoto
patent: 5086413 (1992-02-01), Tsuboi
patent: 5111433 (1992-05-01), Miyamoto
patent: 5151881 (1992-09-01), Kajigaya
patent: 5257231 (1993-10-01), Masuda

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