Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-02-01
2002-09-10
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000, C438S015000, C438S016000, C438S018000, C257S048000, C257S797000, C257S401000, C324S765010, C324S763010
Reexamination Certificate
active
06448098
ABSTRACT:
TECHNICAL FIELD
This invention relates to integrated circuit fabrication, and more particularly to a mechanism for detecting undesired connection between conductive structures within multiple layers on a semiconductor wafer during fabrication of an integrated circuit.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die potentially leads to a higher number of operational IC die fabricated on a semiconductor wafer. Such advantages are a driving force to constantly scale down IC dimensions.
In addition, as IC dimensions are scaled down, multiple layers of conductive structures (such as metal lines for example) are used since stacking of the metal lines leads to a more compact integrated circuit on a semiconductor wafer. As IC dimensions are further scaled down, the integrated circuit is designed with smaller space that separates the structures of the multiple layers on a semiconductor wafer. However, interference and diffusion effects during photolithography processes for patterning these structures of the multiple layers on the semiconductor wafer may make these structures larger. Thus, as IC dimensions are further scaled down, misalignment between the multiple layers of conductive structures results in higher probability of undesired overlap and contact between conductive structures of multiple layers on the semiconductor wafer.
Referring to
FIG. 1A
, a cross sectional view is shown of multiple layers of metal lines on a semiconductor wafer
102
. A top metal line
104
is within a top layer, and a bottom metal line
106
is within a bottom layer that is adjacent a layer of insulating material
108
that is deposited on the semiconductor wafer
102
. The top metal line
104
is typically surrounded by a first insulating material
110
within the top layer. The bottom metal line
106
is also typically surrounded by a second insulating material
112
within the bottom layer.
An interlevel of insulating material
114
is disposed between the top layer and the bottom layer for separating the top layer from the bottom layer. A via structure
116
is typically fabricated within the interlevel of insulating material
114
. The via structure
116
makes contact with the top metal line
104
and couples the top metal line
104
to another structure within the bottom layer. In
FIG. 1A
, the via structure
116
contacts a landing pad
118
within the bottom layer.
Referring to
FIG. 1A
, with proper alignment of the top layer to the bottom layer on the semiconductor wafer
102
, the via structure
116
does not connect to the bottom metal line
106
. In turn, the top metal line
104
is not connected to the bottom metal line
106
for proper operation of the integrated circuit having the top metal line
104
and the bottom metal line
106
.
However, as IC dimensions are further scaled down, misalignment between the top layer, the interlevel of insulating material having the via structure
116
, and the bottom layer results in higher probability of undesired overlap and contact between conductive structures. Thus, referring to
FIG. 1B
, the top layer having the top metal line
104
and the interlevel having the via structure
116
may be misaligned with the bottom layer having the bottom metal line
106
by being shifted too much to the left. As a result, the via structure
116
undesirably makes contact with the bottom metal line
106
. In turn, the top metal line
104
is then undesirably connected to the bottom metal line
106
through the via structure
116
. Such a short circuit between the top metal line
104
and the bottom metal line
106
may result in an inoperative integrated circuit having the top metal line
104
and the bottom metal line
106
.
In addition, as IC dimensions are scaled down, the proximity effect whereby an integrated circuit structure may be fabricated with larger than intended dimensions becomes a greater contributor to undesired connection between the multiple layers of the conductive structures.
Nevertheless, scaling down of IC dimensions is highly desirable. Thus, a mechanism is desired for checking for undesired connection between multiple layers of conductive structures during diagnostic testing of a semiconductor wafer having integrated circuits fabricated thereon. Such a diagnostic determination helps to screen out faulty semiconductor wafers having undesired connection between conductive structures within multiple layers such that time is not wasted on further testing of such faulty semiconductor wafers. Moreover, such a diagnostic determination easily identifies the mechanism causing the integrated circuits to be inoperative such that corrective actions may be taken during fabrication of such integrated circuits.
SUMMARY OF THE INVENTION
Accordingly, the present invention is a device and apparatus for detecting undesired connection between conductive structures within multiple levels on a semiconductor wafer during fabrication of an integrated circuit on the semiconductor wafer.
Generally, the present invention includes a first conductive structure fabricated within the first layer on the semiconductor wafer and a second conductive structure fabricated within the second layer on the semiconductor wafer. The present invention also includes an interlevel of an insulating material disposed between the first layer and the second layer for separating the first layer from the second layer. The present invention further includes a contact structure of conductive material disposed within the interlevel of the insulating material. The contact structure is connected to the first conductive structure. In addition, the present invention includes a detector for determining when the contact structure is undesirably connected to the second conductive structure.
The contact structure is undesirably connected to the second conductive structure from at least one of: sufficient misalignment of at least one of the first layer, the second layer, and the interlevel of insulating material; sufficient proximity effect on at least one of the first conductive structure, the second conductive structure, and the contact structure; and sufficient defects in at least one of the the second layer and the interlevel of insulating material.
In one embodiment of the present invention, the detector for determining when the contact structure is undesirably connected to the second conductive structure includes a voltage generator for applying a voltage between the first conductive structure and the second conductive structure. Furthermore, a current meter measures a current flowing through the first conductive structure and the second conductive structure from the voltage being applied between the first conductive structure and the second conductive structure. This measured current is substantially zero when the contact structure does not make contact with the second conductive structure, and this measured current is greater than zero when the contact structure is undesirably connected to the second conductive structure.
In another embodiment of the present invention, the first conductive structure has a comb structure with a respective contact structure connected to each tooth of the comb structure. In that case, the second conductive structure surrounds the three sides of the respective contact structure. With such a configuration of the first conductive structure and the second conductive structure, misalignment of the first layer with the second layer may be detected for a plurality of directions of misalignment.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.
REFERENCES:
patent: 4984061 (1991-01-01), Matsumoto
patent: 5
Choi Monica H.
Fahmy Wael
Maldonado Julio J.
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