Detection circuit for mixed asynchronous and synchronous...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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C711S100000, C711S105000, C711S106000, C711S111000, C711S157000, C711S158000, C711S166000, C327S166000, C327S176000, C327S026000, C365S194000, C365S222000

Reexamination Certificate

active

08082413

ABSTRACT:
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

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