Detecting short circuits within an integrated circuit design

Details Detecting short circuits within an integrated circuit design Detecting short circuits within an integrated circuit design

2007-07-03

2007-07-03

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11086964

ABSTRACT:
In one embodiment, the present invention includes a method for obtaining a physical layout for an integrated circuit (IC) design of a substrate having at least one of an n-well and a deep n-well; and extracting a layout netlist for the IC design from the physical layout by identifying the substrate as a single region. In such manner, short circuits isolated by the n-well or the deep n-well can be detected.

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U.S. Appl. No. 10/902,233, filed Jul. 29, 2004, entitled “Integrated Circuit Having Features to Limit Substrate Current”.
Cadence: Layout Versus Schematic (LVS) Verification. http://www.seas.upenn.edu/˜eecad/cadence/lvs.html. Mar. 15, 2003.

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