Detecting faults in dual port FIFO memories

Details Detecting faults in dual port FIFO memories Detecting faults in dual port FIFO memories

1999-09-16

2004-06-29

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06757854

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory devices and particularly to dual port first-in-first-out (FIFO) memory devices. More particularly, the present invention relates to detecting faults in dual port FIFO memory devices.
BACKGROUND OF THE INVENTION
FIFO Memories
Fast, efficient testing is an important step in manufacturing memory chips, and the price paid for recent advances in semiconductor technology has been a lengthier and more complicated testing process. Consequently, procedures that test the memory thoroughly, quickly, and without complication are highly prized. One type of memory chip is the first-in-first-out (FIFO) memory, commonly referred to simply as a “FIFO.” Like conventional memories, a FIFO performs read operations, which retrieve data from the FIFO, as well as write operations, which store data in the FIFO. Unlike conventional memories which permit read and write operations in any desired order at specified memory locations, the FIFO reads out data in the same order the data was written. Suppose, for example, that a first data value is written to the FIFO, followed by a second data value and then a third data value. The first read operation performed on the FIFO will return the first data value. If a second read operation is performed, then the FIFO will retrieve the second data value, and if a third read operation is performed, the FIFO will retrieve the third data value. After the third and final data value is read from the FIFO, no more read operations can occur until another value is written to the FIFO, and thus the FIFO is said to be “empty.” The FIFO also may become full if all of the memory locations are written without reading any data. When full, the FIFO prohibits write operations, so data must first be read out of the FIFO to make room for further write operations.
Multiport Architecture
A common feature of current memories, including many FIFO's, is the presence of multiple “ports,” or gateways that allow data to be read from and/or written to the memory. The ports on a multiport memory are designed to function independently, allowing memory accesses to multiple locations at the same time. Prior memories, which had a single memory port, could only read or write data in one memory location at a time. Multiple ports thus increase memory throughput, or the speed at which data can be transferred to and from memory. FIFO's often include two ports: one port that writes data, and one port that reads data. Accordingly, data values can be read and written concurrently.
FIG. 1
illustrates a representative multiport memory device
150
, comprising an array of memory cells
100
,
101
,
109
,
110
,
111
,
119
,
190
,
191
and
199
. As shown in
FIG. 1
, the cells are organized into R rows and C columns, where R and C can be any values. Cells
100
and
101
represent the first two columns of the first row, and cell
109
represents the last (or C−1
th
) column of the first row. Similarly, cells
110
,
111
, and
119
represent the first, second, and last columns of the second row. In the final (or R−1
th
) row, cells
190
,
191
, and
199
occupy the first, second, and last columns, respectively. Each memory cell is capable of storing an electric charge, and the charges can be manipulated to store and recall data through the use of special control circuitry (not shown) in the memory
150
. Each memory cell can represent one of two values, depending on whether or not the cell holds a charge. The values 1 and 0 are often used to represent the charged and uncharged states, respectively, although the reverse may be true. Because the cells can hold either of two possible values, the memory device
150
is called a “binary” device, and the cell data values are known as binary digits, or “bits.”
To fetch and store the data values, the memory device
150
includes signals known as “word lines” and “bit lines” that couple to the cells. The word lines connect cells in the same row and are used to activate the cells along one row at a time. The bit lines connect cells in the same column and are used to carry data to and from the activated cells. In a multiport device, each port has its own word lines and bit lines. The memory device
150
in
FIG. 1
is shown with P ports, where P can be any number but is typically less than or equal to 11 under current technology.
The first port includes a first word line W
10
that connects the cells
100
,
101
, and
109
in the first row; a second word line W
11
that connects the cells
110
,
111
, and
119
in the second row; and additional word lines for the other rows, including a word line W
P(R−1)
that connects the cells
190
,
191
, and
199
in the final row. The first port also comprises a first bit line B
10
that connects the cells
100
,
110
, and
190
in the first column; a second bit line B
11
that connects the cells
101
,
111
, and
191
in the second column; and additional bit lines for the remaining columns, including a bit line B
p(C−1)
that connects the cells
109
,
119
, and
199
in the final column. To read data from the first row of cells through the first port, for example, the word line W
10
is activated. In response to activating the word line W
10
, cells
100
and
101
place their data values onto bit lines B
10
and B
11
, respectively. Similarly, the other cells in the first row drive their bit lines on the first port with the stored data, including cell
109
, which drives bit line B
1(C−1)
with the data value stored in cell
109
.
The word lines and bit lines also can be used to store data in the cells. To write data to the cells in the second row through the first port, for example, the word line W
11
is asserted to activate the cells in the second row, including cells
110
,
111
, and
119
. At the same time, the values being stored are placed on the bit lines belonging to the first port, including bit lines B
10
, B
11
, and B
1(C−1)
. In response, the cells on the second row store the data encoded by the bit lines. Cell
110
thus stores the value of bit line B
10
, cell
111
stores the value of bit line B
11
, and cell
119
stores the value of bit line B
1(C−1)
.
Similarly, the remaining ports include word lines and bit lines for accessing the memory cells. Ideally, one port can access any row of cells while another port is accessing another row of cells without interference between the two ports, since the ports do not share word lines and bit lines.
FIFO Architecture
FIG. 2
illustrates a representative dual port FIFO memory
250
comprising an array of memory cells
230
which are interfaced via a write bus, a read bus, a write enable line, and a read enable line. The FIFO
250
comprises two ports: a read-only port and a write-only port. Accordingly, the FIFO
250
can execute a read and a write operation in parallel. The memory cells
230
are arranged in words of four bits each, although each word may comprise any number of bits. Memory cells
200
-
203
represent the lowest address in the array, followed by the memory word formed by cells
210
-
213
and then the memory word formed by cells
220
-
223
. Memory cells
280
-
283
form the next to last memory word, while memory cells
290
-
293
form the final memory word. Letting N represent the total number of memory words in the array
230
, cells
200
-
203
represent the 0
th
word (or “address
0
”), and cells
290
-
293
represent the N−1
th
word (or “address N−1”). The FIFO
250
also includes a full flag
252
which is set to logic 1 if the FIFO
250
becomes full, and an empty flag
256
which is set to logic 1 if the FIFO
250
is empty. To perform a read operation, the read enable line must be asserted. If a read operation is initiated, or attempted, when the read enable line is deasserted, then the FIFO will not perform the read operation. Similarly, if a write operation is initiated when the write enable line is not asserted, the FIFO will not perform the write operation. The write enable line must be

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