Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-12-09
2000-11-21
Wright, Norman M.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 4, 714 18, 714 49, H02H 305
Patent
active
061516899
ABSTRACT:
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
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Bunton William Patterson
Coddington John Deane
Garcia David J.
Krause John C.
Meredith Susan Stone
Tandem Computers Incorporated
Wright Norman M.
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