Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1994-10-06
1997-02-18
Chin, Wellington
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375376, 370516, H04L 700, H04L 2300
Patent
active
056047738
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to a method for suppressing pointer phase jitter in a desynchronizer comprising a data buffer means; a data buffer write address counter controlled by a write clock; a data buffer read address counter controlled by a read clock; and a phase-locked loop for phase-locking the read clock to the write clock.
BACKGROUND OF THE INVENTION
The CCITT recommendations G.707, G.708 and G.709 specify a synchronous digital hierarchy SDH, which enables the multiplexing of the signals of existing PCM systems, such as 2, 8, 34 and 140 Mbit/s, into a synchronous frame of 155 Mbit/s called STM-1 (synchronous transfer module). The structure of the STM-1 frame is illustrated in FIG. 1. The frame is usually shown as a unit comprising nine lines each having 270 bytes. The first nine bytes on each line contain a section overhead and AU pointer bytes. The remaining portion of the transfer frame STM-1 contains one or more administration units AU. In this specific case, there is an administration unit AU-4 of the highest level, in which a virtual container VC-4 similarly of the highest level is placed, and e.g. a 139264 kbit/s plesiochronous information signal can be mapped directly in the virtual container VC-4. Alternatively, the transfer frame STM-1 may contain several lower-level administration units AU in each one of which a corresponding virtual container VC of the lowest level is placed. In FIG. 1, the VC-4 comprises a 1-byte path overhead POH and a 240-byte information bit group at the start of both of which a special control byte is placed. Some of the control bytes are used, e.g. for performing interface justification in connection with mapping when the rate of the information signal to be mapped deviates to some extent from its nominal value. Mapping of the information signal into the transfer frame STM-1 is described, e.g. in the patent applications AU-B-34639/89 and FI-914746.
Each byte in the unit AU-4 has a position number. The above-mentioned AU pointer contains the position of the first byte of the container VC-4 in the unit AU-4. In addition, by means of the pointers, so-called positive or negative pointer justifications can be performed at the different locations of the SDH network. If a VC having a certain clock frequency is applied to a network node operating at a clock frequency lower than the above-mentioned clock frequency of the VC, the data buffer will be filled up. This requires negative justification: one byte is transferred from the received VC into the overhead section, while the pointer value is decreased by one.
If the rate of the received VC is lower than the clock rate of the node, the data buffer tends to be emptied, which calls for positive justification in which a stuff byte is added to the VC and the pointer value is incremented by one.
Bit justification (interface justification) used in mapping as well as pointer justification cause phase jitter, which should be compensated for by the desynchronizer on leaving the SDH network. Phase jitter and its compensation are described, e.g. in Simulation Results and Field Trial Experience of Justification Jitter, Ralph Urbansky, 6th World Telecommunication Forum, Geneva, Oct. 10-15 1991, International Telecommunication Union, Part 2, Vol III, p. 45 to 49.
For this purpose, the prior art desynchronizers comprise a data buffer with an associated analog phase-locked loop (PLL) which phase-locks the read clock of the data buffer to the write clock. As the PLL operates in the same way as a lowpass filter, it removes jitter except for jitter components of the lowest frequency. For instance, the pointer justification of the SDH typically generates much more intensive jitter components than bit justification as individual phase discontinuities in the pointer justification are e.g. 8 or 24 frame intervals UI and as the frequency of occurrence of phase discontinuities induced by pointer justifications may represent a very low frequency difficult to filter in the PLL of the desynchronizer. Adequate suppression of poin
REFERENCES:
patent: 4095053 (1978-06-01), Duttweiler et al.
patent: 4811340 (1989-03-01), McEachern et al.
patent: 4996698 (1991-02-01), Nelson
patent: 5052025 (1991-09-01), Duff et al.
patent: 5268935 (1993-12-01), Mediavilla et al.
patent: 5457717 (1995-10-01), Bellamy
Chin Wellington
Loomis Paul
Nokia Telecommunications Oy
LandOfFree
Desynchronizer and method for suppressing pointer jitter in a de does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Desynchronizer and method for suppressing pointer jitter in a de, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Desynchronizer and method for suppressing pointer jitter in a de will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1607635