Deskewed clock distribution network with edge clock

Details Deskewed clock distribution network with edge clock Deskewed clock distribution network with edge clock

1995-10-16

1998-01-27

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 41, 326 47, 326101, H03K 19177, H03K 1900

Patent

active

057125791

ABSTRACT:
A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip. An edge clock is provided that is not deskewed and is directly coupled to an edge clock distribution system along the left and right edges of the IC to supply a clock signal to an entire edge or half of an edge with less delay relative to the deskewed clock. Also, a super fast edge clock is provided for very high speed circuits.

REFERENCES:
patent: 5140184 (1992-08-01), Hamamoto et al.
patent: 5391942 (1995-02-01), El-Ayat et al.
patent: 5397943 (1995-03-01), West et al.
patent: 5467033 (1995-11-01), Yip et al.
patent: 5481209 (1996-01-01), Lim et al.

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