Static information storage and retrieval – Systems using particular element – Magnetic thin film
Reexamination Certificate
2001-12-12
2004-04-13
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetic thin film
C365S158000, C365S209000
Reexamination Certificate
active
06721203
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data storage and more particularly to utilizing a reference cell to increase a read accuracy of memory cells from Magnetic Random Access Memory (MRAM) units.
2. Description of the Prior Art
A wide range of presently available media for data storage vary in several attributes including access speed, duration of reliable storage, and cost. Static Random Access Memory (SRAM) is the storage medium with the best access speed for the cost in applications such as cache memories. However, SRAM is volatile, meaning that it only maintains storage while power is continuously applied. Accordingly, computer users endure lengthy waits when they power-up their computers while substantial amounts of data are written from non-volatile but slow media, such as magnetic disks, into much faster random access memory (SRAM).
Flash memory has been proposed as an alternative to SRAM. Flash memory is a solid-state storage medium that provides moderate access times and is non-volatile. However, flash memory has the disadvantage that it has a limited lifetime, on the order of one million cycles per cell, after which it is no longer possible to write to a cell. This lifetime is orders of magnitude too short for a random access memory in most modern computing systems.
Another solid-state storage medium is Magnetic Random Access Memory (MRAM), which employs a Magnetic Tunnel Junction (MTJ) formed of layers of magnetic material.
FIG. 1
shows a cross-section of a prior art MRAM unit
10
including an MTJ
12
formed of a pinned-layer
14
and a free-layer
16
, which are magnetic layers typically formed of ferromagnetic materials, and a thin dielectric layer
18
disposed between layers
14
and
16
. Pinned-layer
14
has a magnetic moment orientation
20
that is fixed from rotating, while free-layer
16
has a magnetic moment orientation
22
that is free to rotate in response to external magnetic fields. Methods of pinning a pinned-layer
14
are well known in the art and include the use of an adjacent antiferromagnetic layer (not shown).
In an MRAM unit
10
, a bit of data is encoded in the direction of the magnetic moment orientation
22
of the free-layer
16
relative to the magnetic moment orientation
20
of the pinned-layer
14
. As is well known in the art, when the two magnetic moment orientations
20
,
22
are parallel the resistance measured across the MTJ
12
is relatively low, and when the two magnetic moment orientations
20
,
22
are antiparallel the resistance measured across the MTJ
12
is relatively high. Accordingly, the relative state of the magnetic moment orientations
20
,
22
, either parallel or antiparallel to one another, can be determined by reading the resistance across the MTJ
12
with a read current. Typical read currents are on the order of 1-50 &mgr;A.
In an MRAM unit
10
, the state of the bit, parallel or antiparallel and representing 0 or 1, for example, is varied by applying a write current I
W
, typically on the order of 1-25 mA, through two conductors, a bit line
24
and a digit line
26
, situated proximate to the MTJ
12
. The intensity of the write current applied to the bit line
24
may be different than that applied to the digit line
26
. The bit line
24
and the digit line
26
cross one another at right angles above and below the MTJ
12
. As is well known in the art, although the pinned-layer
14
is depicted in
FIG. 1
as nearer to the bit line
24
, an MRAM unit
10
also functions with the pinned-layer
14
nearer to the digit line
26
.
As is well known, a magnetic field develops around an electric current in a wire. Accordingly, two magnetic fields arise when write currents I
W
are simultaneously applied to both the bit line
24
and the digit line
26
. The two magnetic fields combine at the free-layer
16
to determine the magnetic moment orientation
22
. The magnetic moment orientation
22
of the free-layer
16
is made to alternate between the parallel and antiparallel states by alternating the direction of the write current I
W
in either the bit line
24
or the digit line
26
. Alternating (by a write control circuit, not shown) the direction of the write current I
W
in one of the lines
24
,
26
reverses the direction of the magnetic field around that conductor and thereby reverses the direction of the combined magnetic field at the free-layer
16
.
In an MRAM unit
10
, the state of the bit is read by passing a read current I
R
through the MTJ
12
. In these designs a transistor
30
is used to allow the read current I
R
to flow through the MTJ
12
during a read operation while preventing the write current I
W
from flowing through the MTJ
12
during a write operation.
A control signal is required to determine which direction the reversible write current I
W
will flow. Another control signal is required to change the state of the transistor
30
for read and write operations.
A voltage signal V
S
is produced by sending a read current I
R
through the MTJ
12
. For reading an MTJ MRAM cell, the signal V
S
from MTJ
12
is compared with a signal V
REF
from a reference cell at a comparator
200
utilizing amplifier
210
as shown in FIG.
2
.
A typical memory cell
300
as shown in
FIG. 3A
includes a current source
310
, an MTJ device
320
, an output
330
coupled to a bit line, and a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) switching transistor
340
. A resistance of the MTJ device
320
can either be set to a logical “0” state, resulting in a low resistance setting, R, or set to a logical “1” state, resulting in a high resistance setting, R+&Dgr;R. Consequently, the signal V
S
for a low resistance state is
V
S
(0)=
V
MOS
+I
R
R
whereas the signal V
S
for a high resistance state is
V
S
(1)=
V
MOS
+I
R
(
R+&Dgr;R
)
In both equations, V
MOS
is a voltage drop across a drain and a source of the MOSFET switching transistor
340
. It will be understood that the MOSFET switching transistor
340
may also be of another transistor type, such as a JFET (Junction Field Effect Transistor) or bipolar transistor.
FIG. 3B
shows a reference cell
350
including a current source
360
, an MTJ device
370
having a resistance R
2
, a reference output
380
coupled to a bit line, and a MOSFET switching transistor
390
. To obtain the best reading performance coupled with high reliability and accuracy, an output signal V
REF
from reference cell
350
should have a median value between V
S
(1) and V
S
(0). For V
REF
to be between V
S
(1) and V
S
(2), R
2
would need to be between R and R+&Dgr;R. Ideally, this leads to
V
REF
=
V
MOS
+
I
R
R
2
V
REF
=
V
s
(
1
)
+
V
s
(
0
)
2
V
REF
=
V
MOS
+
I
R
(
R
+
Δ
R
)
+
V
MOS
+
I
R
R
2
V
REF
=
2
V
MOS
+
2
I
R
R
+
I
R
Δ
R
2
V
REF
=
V
MOS
+
I
R
(
R
+
Δ
R
2
)
Therefore, the resistance R
2
of reference cell
350
should preferably be
R
+
Δ
R
2
.
Since a memory cell has a resistance of either R or R+&Dgr;R, one approach to producing a reference cell with a resistance of
R
+
Δ
R
2
is to fabricate a reference cell as if it were a memory cell with a slightly different size or shape. However, if fabrication process parameters change, the resistance of a reference cell may not change commensurately with the resistance of a memory cell. This change in the reference cell resistance may result in an inaccurate reference signal. Consequently, the possibility of read error increases (e.g., reading a logical “0” from a memory cell set to a high state (logical “1”), or vice versa) and read sensitivity (the ability to discern an actual logic state) decreases.
Accordingly, what is desired is a reference cell designed and fabricated with the same shape and size as a memory cell but arranged in such a way so as to provide a summed effective resistance of
R
+
Δ
R
2
.
SUMMA
Gibbons Matthew R.
Qi Qiuqun
Shi Xizeng
Carr & Ferrell LLP
Lebentritt Michael S.
Nguyen Hien
Western Digital (Fremont) Inc.
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