Designing integrated circuit gate arrays using programmable...

Details Designing integrated circuit gate arrays using programmable... Designing integrated circuit gate arrays using programmable...

1998-12-14

2001-10-30

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S037000, C326S041000, C326S039000, C326S047000

Reexamination Certificate

active

06311316

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit design methods, and more particularly to application specific integrated circuit design methods.
BACKGROUND OF THE INVENTION
Integrated circuit designers frequently choose application specific integrated circuit (ASIC) technology when designing integrated circuits to perform unique and customized functions. This is because ASIC technology provides designers with comprehensive tools to customize logic to perform specialized and multiple functions on a single integrated circuit substrate or chip, instead of the multiple chips which typically would be required in the event standardized circuit technology was employed. As will be understood by those skilled in the art, ASICs may be generated in many different ways and have many different designations based on the methods used to design and/or manufacture them. The most time consuming method, but often the one that yields the smallest chip size and/or best performance, is the “full-custom” designed ASIC. These ASICs are often designed entirely from scratch at the transistor level with only occasional use of previously designed circuit “blocks” which are typically referred to as cells, standard cells, or macrocells. Because of this comprehensive approach, custom designed ASICs typically require the creation of an entire design database and test methods (including custom test vectors). A complete set of customized fabrication masks is also typically required for fabrication. These requirements typically make the design and fabrication of custom ASICs very time consuming and expensive when generating prototype devices and when iterating through design changes. Alternative ASIC design methodologies include the use of standard cell technology, which differs from full custom design in that multiple cells or macrocells that have been previously designed are utilized. These cells are selected from libraries of cells for their applicability to the design, and placed and routed with software that is well known in the art. The final circuit then has no fewer custom mask layers than the full custom design method. However, this method does have advantages over the full custom design method in the time required to complete a design, because the elementary level of cell design is only done once to create the libraries, and this work can be reused in multiple subsequent designs.
Alternative application specific integrated circuit design technologies which typically do not incur the time and expense penalties associated with full custom ASICs include gate array technology. Gate array technology typically utilizes the building blocks of logic gates and/or memory devices as resources to minimize design time and cost. This extensive use of blocks enables the gate array designer to focus more on the routing of connections (e.g., metal wiring and interconnects) between these blocks and less on the design and operation of the individual logic gates and other low-level devices. Here, the designer may be able to reduce the number of custom mask layers that must be generated for fabrication because typically only the uppermost masking layers are specific to a particular design. On the other hand, the base masking layers that determine the logic and memory blocks are typically identical for a variety of designs. With these savings comes a penalty since only certain types and sizes of logic gates are typically available to choose from and constraints on the placement of such gates may not always lead to a device having ideal characteristics.
Gate array technology also provides a reduction in the time and expense associated with making design changes through an iterative process. This is because less than all mask layers are involved in any design change at any level, as opposed to the full-custom ASIC design case where design changes may require a change to all mask layers. Notwithstanding these benefits, gate array technology may still require some relatively expensive custom tooling for the upper level masks. Moreover, design checking in physical silicon cannot take place without processing one or more wafers through multiple fabrication steps including deposition, masking and etching, for example, just like full-custom ASIC technology. The terms ASIC and gate array are meant to be interchangeable for the purposes of this disclosure. ASIC or gate array can refer to fully-custom integrated circuits, or semi-custom integrated circuits, including standard cell integrated circuits.
Referring now to
FIG. 1
, a flow diagram of operations
100
performed when designing a full-custom ASIC will be described. Although the flow diagram displays many decision points and their associated unacceptable paths, the following description does not attempt to elaborate on all the unacceptable paths. As illustrated, a design specification of a desired integrated circuit is initially provided, Block
102
, and then from this a HDL/schematic description of the integrated circuit is entered into a design system, Block
104
, to generate a complete HDUschematic description, Block
106
. From this HDUschematic description, an operation is performed to simulate the functional operation of the integrated circuit, Block
108
. The simulation is then checked for accuracy, Block
110
. If the simulation is correct, an operation is performed to synthesize logic and generate a logic netlist, Blocks
112
and
114
. The synthesis of the logic may require ASIC logic primitives and resources, Block
113
, and user synthesis constraints, Block
111
. A check may then be performed to determine whether the integrated circuit will receive an internal scan test, Block
116
. If so, scan elements can be added to the logic netlist, Block
118
. Then, with the addition of ASIC element timing estimates, Block
115
, an operation is performed to simulate the timing of the integrated circuit, Block
121
. The timing simulation is then checked for accuracy, Block
123
. If the simulation is correct, a logic placement and signal routing operation will be performed, Block
120
, based on a set of user routing and logic placement constraints, Block
150
, and ASIC logic resources and routing resources and constraints, Block
117
. From this placement and routing operation, a routed netlist will be generated, Block
122
.
A timing extraction operation (e.g., parasitic R and C extraction operation) may then be performed, Block
124
, to generate timing parameters, Block
126
. The routed netlist and timing parameters are then used to perform another timing simulation, Block
128
, which takes into account the actual placement of gates, devices, etc., and interconnect nets which link these devices together. A check is then performed to determine whether the simulation is acceptable, Block
130
. If the simulation is acceptable, test vectors are created, Block
140
. Operations are also performed to create mask-making data, Block
132
. The mask-making data, Block
134
, is then used to create masks, Block
136
. A prototype of the full-custom ASIC device is then fabricated, Block
138
. An operation is then performed to test and evaluate the device and/or system, Block
142
. If the test results are acceptable, then the design is complete. However, if the test results are not acceptable, then a check is made to determine whether the HDL/schematic description of the invention (i.e. logic) needs to be modified, the routing and placement needs to be modified, or the synthesis constraints need to be modified, Block
144
. If the HDUschematic description needs to be modified, Block
146
, then essentially all the above-described steps and operations will need to be repeated. If the synthesis constraints need to be modified, Block
119
, then the majority of the above-described steps and operations will need to be repeated from the logic synthesis step, Block
112
. But, if only the routing and placement constraints need to be modified, Block
148
, then the process can resume at the logic placement and signal routing step, Block
120
.
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