Designing and fabrication of a semiconductor device

Details Designing and fabrication of a semiconductor device Designing and fabrication of a semiconductor device

2006-01-18

2008-09-09

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C257S499000

Reexamination Certificate

active

07424688

ABSTRACT:
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 μm or less are excluded from the optimization.

REFERENCES:
patent: 6584095 (2003-06-01), Jocobi et al.
patent: 2001/0026992 (2001-10-01), Mori et al.
patent: 2003/0226127 (2003-12-01), Idani
patent: 2005/0160381 (2005-07-01), Idani et al.
patent: 2005/0224358 (2005-10-01), Kwak et al.
patent: 2007/0061768 (2007-03-01), Travis et al.
patent: 2001-7114 (2001-01-01), None
patent: 2003-347406 (2003-12-01), None

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