Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-21
2006-03-21
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07017133
ABSTRACT:
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 μm or less are excluded from the optimization.
REFERENCES:
patent: 6584095 (2003-06-01), Jacobi et al.
patent: 2003/0226127 (2003-12-01), Idani
patent: 2001-7114 (2001-01-01), None
patent: 2003-347406 (2003-12-01), None
Idani Naoki
Karasawa Toshiyuki
Nanjo Ryota
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
Whitmore Stacy A.
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