Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2011-06-28
2011-06-28
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S115000, C703S013000
Reexamination Certificate
active
07971177
ABSTRACT:
A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.
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Chen Ming Shang
Ku Shaw Hung
Lu Wenpin
Wu Chia Wei
Garbowski Leigh Marie
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
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