Design techniques for analyzing integrated circuit device...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06951002

ABSTRACT:
An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.

REFERENCES:
patent: 6523159 (2003-02-01), Bernstein et al.
patent: 6721924 (2004-04-01), Patra et al.
Hough et al., “New Approaches for On-Chip Power Switching Noise Reduction”, May 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 133-136.
Chen et al., “On-Chip Decoupling Capacitor Optimization for High-Performance VLSI Design”, May 1995, IEEE, Proceedings of Technical Papers, International Symposium on VLSI Technology, Systems, and Applications, pp. 99-103.

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