Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-27
2003-02-04
Nguyen, Cuong Quang (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06516446
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computed aided design (CAD) system for a flip chip semiconductor device, and more particularly to a design system which is capable of designing a flip chip semiconductor device in a smaller time length.
2. Description of the Related Art
In recent years, the higher integration levels of semiconductor chips has lead to smaller and thinner semiconductor devices. As a result, further increases in the performance and the speed of electronic equipment become possible. In addition, new packages are developed in response to the demands generated by this type of higher performance, lighter weight, and higher speed electronic equipment. One such example is the appearance of packages using flip chip systems (FCBGA: flip chip ball grid array) which enable high density packaging.
In the design and development of a flip chip semiconductor integrated circuit, computer aided design (CAD) is used for preparing the layout while various processing is executed.
FIG. 1
is a flowchart showing a conventional design system for a flip chip (flip chip system) semiconductor integrated circuit. This design system includes processing for preparing a flip chip layout in advance, and processing for preparing an internal circuit layout in advance.
In the processing for preparing the flip chip layout, first, layout parts
710
for the flip chip system are prepared, and then at step
711
, electrode pads (PAD) including both power source pads and signal pads are positioned using the CAD system. Subsequently, at step
712
, power source lines are arranged in the internal circuit area including internal circuit blocks (internal cell blocks). Then, at step
713
, connections are made between the power source lines of the internal circuit area and the power source pads, and then at step
714
the layout design is tested. If the test results are unsatisfactory then manual modifications are made at step
715
, whereas if the test results are satisfactory, the layout is accepted as a flip chip layout
716
.
In contrast, in the processing for preparing a layout diagram for the internal circuit, layout information, terminal information, and the like for the internal circuit are stored, in advance, in a layout library
701
. Subsequently, at step
702
, the necessary information is retrieved from the layout library
701
, and I/O cells are positioned based on chip size and information for each of the input and output terminals.
The internal circuit is positioned at step
703
, and then at step
704
, power source lines are arranged within the positioned internal circuit. At step
705
, internal circuit blocks are positioned for macro blocks, RAMs, internal cellc blocks, and the like, and then at step
706
, signal lines are arranged within the internal circuit. At step
707
, a test is performed of the circuit characteristics of the internal circuit, and if the test results are unsatisfactory then the process proceeds to step
708
where manual modifications are made. In contrast, if the test results are satisfactory, then the layout is retained as an internal circuit layout
709
.
Subsequently, at step
717
, the flip chip layout
716
and the internal circuit layout
709
are combined by superposition of the layout data. Then, at step
718
, connections are made between the power source lines of the internal circuit area and the power source pads of each of the positioned internal circuit blocks, as well as between the signal pads and the I/O cells. After modifications are applied to either the electrode pads including the signal pads and the power source pads or the power source lines at step
719
, a test of the circuit characteristics is performed at step
720
. If the test results are unsatisfactory, the process jumps to either step
708
or step
715
where the corresponding modification processing is conducted. In contrast, if the test results are satisfactory, then the layout is accepted as a flip chip layout diagram
721
.
As follows is a more detailed description of the modifications of step
719
. For example, if a macro block including interconnect lines which are formed as the same level layer as the power source lines is positioned within the flip chip layout as an internal circuit block, then in order to prevent a short circuit failure with the power source lines, the interconnect lines require some type of modification, such as cut-off or removal of portions of some interconnect lines.
FIGS. 2A
to
2
C are schematic diagrams showing processing during such a manual modification step.
FIG. 2A
shows arrangement of the power source lines including VDD lines
901
and GNG lines
902
in the internal circuit area,
FIG. 2B
shows the stage after positioning of a macro block
903
including interconnect lines having the same level with the power source lines, and
FIG. 2C
shows the stage after the deletion of the unnecessary portions of the power source lines. In actuality, although electrode pads would also be arranged in
FIGS. 2A
to
2
C, they have been omitted therein for the sake of simplicity.
In
FIG. 2A
, a CAD system is used to alternately provide VDD lines
801
and GND lines
802
, which function as the power source lines. Then, as shown in
FIG. 2B
, a macro block
803
, a portion of which overlaps the sections of the VDD lines
801
and the GND lines
802
in the same level, is arranged in the CAD system. As shown in
FIG. 2C
, the sections of the VDD lines
801
and the GND lines
802
which pass through the macro block
803
are deleted manually.
FIGS. 3A
to
3
C show another example of a conventional manual modification, wherein electrode pads are modified.
FIG. 3A
shows electrode pads positioned within the internal circuit area,
FIG. 3B
shows the stage wherein a RAM is superposed thereon, and
FIG. 3C
shows the stage after deletion of the electrode pads overlapping with the RAM.
In
FIG. 3A
, the CAD system is used to arrange VDD pads
901
and GND pads
902
, which function as power source pads in the internal circuit area, alternately in a matrix. During an actual flip chip system process, assuming the case that balls (of Pb—Sn based solder, for example) which function as the external terminals are mounted onto the electrode pads, if the RAM
903
is positioned directly below the balls
901
and
902
, an á ray emitted from one of the balls
901
and
902
may cause a soft error in the RAM
903
. In view of this soft error, the power source pads
901
and
902
in the flip chip system are prohibited for positioning thereof directly above the RAM
903
, if included in the internal circuit layout, in the layout design. Consequently, the electrode pads, such as
901
and
902
, which overlap with the RAM
903
shown in
FIG. 3B
are deleted, as shown in FIG.
3
C.
As described above, the conventional design system requires a rather complex processing, with the internal circuit layout
709
and the flip chip layout
716
being prepared separately in advance. These two layouts are then superposed, and secondary modifications are performed as required, before the testing process. Tests for design rules and the like also need to be performed individually. In particular, if the test results after the superposition of the two layout data
716
and
709
are unsatisfactory, modifications of the layout data
716
and
709
need to be performed manually, and these manual modifications must then be continued until a satisfactory test result is achieved. As a result, it takes a larger workload and a larger time length in the layout design. Furthermore, because the flip chip layout must be prepared manually for each different chip size, the development of new flip chip system requires larger volumes of data and larger number of development steps.
SUMMARY OF THE INVENTION
The present invention takes the above situation into consideration, with an object of providing a design system for a flip chip semiconductor device, which is capable of reducing the overall design time by reducing the time required for p
Choate Hall & Stewart
NEC Corporation
Nguyen Cuong Quang
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