Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-15
2002-10-15
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06467070
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a design support apparatus for semiconductor devices and, more particularly, to a design support apparatus for semiconductor devices that can arrange non-logic cells easily.
(2) Description of the Related Art
With an increase in clock signal frequencies, the occurrence of electromagnetic radiation in a semiconductor device, such as a large-scale integrated circuit (LSI), is becoming an important problem in recent years.
Conventionally, various methods have been adopted in order to prevent the occurrence of such electromagnetic radiation. The method of reducing the impedance of power supply at a high frequency by adding a decoupling capacitor to a power supply line in an LSI is known as an effective one.
By the way, a decoupling capacitor is an equivalent one consisting of, for example, metal oxide semiconductor field effect transistors (MOS-FET) and can be formed by the same process as with a logic element.
In most conventional methods, therefore, these equivalent capacitors have been treated the same as other logic elements and an automatic layout has been done for them.
Furthermore, not only decoupling capacitors but also many other things, which are not logic elements, are arranged on an integrated circuit chip. Conventionally, arranging and wiring processes on non-logic cells containing these patterns which do not form a logic circuit and on logic cells containing patterns which form a logic circuit have been performed at the same time.
With this method, however, layouts must be done with equivalent capacitors etc. contained. This increases the number of elements for which a layout is done by that of equivalent capacitors etc., so it will take much time to perform a layout process.
In addition, after a layout, performance tests are performed on a semiconductor device by a delay simulation etc. If the tests show that the semiconductor device is not equipped with desired performance, a layout process must be performed again. In this case, the second layout process must be performed on all elements including equivalent capacitors, so it will take much time to perform it.
SUMMARY OF THE INVENTION
In order to address such problems, the present invention was made. In other words, an object of the present invention is to provide a design support apparatus for semiconductor devices that enables to avoid complex and time-consuming design work resulting from the existence of non-logic cells.
In order to achieve the above object, a design support apparatus for semiconductor devices for helping to design semiconductor devices is provided. This design support apparatus for semiconductor devices comprises layout means for doing a layout for logic cells and wiring patterns to connect the logic cells, arranged site detecting means for detecting, after a layout being done by the layout means, an arranged site being a site containing neither the logic cells nor a prohibited area, and non-logic cell arranging means for arranging non-logic cells on the arranged site.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
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Ichinose Shigenori
Kuroda Sachi
Osajima Toru
Sugioka Toshiaki
Dinh Trinh Vo
Fujitsu Limited
Wong Don
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