Electric lamp and discharge devices – Discharge devices having a multipointed or serrated edge...
Reexamination Certificate
2003-03-07
2004-08-03
Patel, Nimeshkumar D. (Department: 2879)
Electric lamp and discharge devices
Discharge devices having a multipointed or serrated edge...
C313S310000, C445S050000
Reexamination Certificate
active
06771011
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and in particular, relates to topographic features of semiconductor devices.
2. Background Information
Semiconductor fabrication techniques usually involve multi-step processes. Some multi-step processes are very expensive because different fabrication techniques or materials are required for each process step. Additionally, the fabrication process for one material might be incompatible with another process due to cross-contamination by dopants or etching materials. Devices created with single-crystal silicon, for example have a much lower yield and a higher failure rate than anisotropic silicon devices. The high heat required for some single-crystal fabrication excludes processing at the end of a manufacturing cycle. Therefore, it is difficult to form devices of high quality and uniformity using single-crystal materials or to combine production of such devices with other semiconductor fabrication processes.
One use of single-crystal semiconductor fabrication is the formation of atomically sharp topographies. Atomically sharp topographies are generally formed using crystallographic etched monolithic films of tungsten, silicon, or diamond-like films. The processes used to create atomically sharp topographies using single-crystal fabrication cannot easily be combined with other semiconductor processes due to high temperatures and other constraints. Atomically sharp topographies are very desirable for several applications.
One use for an atomically sharp object is a field emission structure. Field emission structures are well known in the art and include devices such as field emission microtip electron emitters, area emitters, and Field Effect Transistors (FETs). The term “field emission microtip electron emitter” is interchangeable with Field Emission (FE) electron emitter, microtip emitter, cold-cathode tip emitter, Spindt tip emitter, field tip emitter and tip emitter. The field emission electron emitter is a field effect device that emits charged particles when a voltage potential is applied in a particular manner. The charged particle emissions may be controlled by changing the potential voltage with respect to regions of the device. In general, a microtip field emitter has several components including a substrate or base, an atomically sharp feature known as a tip, emitter tip or microtip, and a bias plane. Fabrication of the atomically sharp emitter microtip has generally required the use of single-crystal materials. There are a number of techniques for creating atomically sharp topographies on a substrate for use in a field emission structure.
Field emission electron emitters are usually formed using photolithographic and lift-off techniques to form atomically sharp topographic features on a monolithic film. The methods used to form emitter microtips include molding, electro-etching and thermal oxidation. An example of several methods for creating field emission emitters.
FIG. 1
is an illustration of a technique for creating microtip emitters. The technique is attributed to the French national laboratory, Laboratoire d'Electronique de Technologie et d'Instrumentation (LETI), and illustrates a method of forming what are generally known as Spindt emitters after Dr. Capp Spindt of the Stanford Research Institute.
FIG. 2
is an illustration of a technique for creating a microtip. The technique of Henry Gray relies on an etched silicon mold that is subsequently used, as a mold for a metal microtip. A substrate of silicon crystal is etched using an anisotropic etching process to form a pyramidal pit to be used as a mold. The silicon mold is deposited with a metal layer then silicon mold is etched away leaving the metal layer with an atomically sharp microtip.
FIG. 3
is an illustration of a technique for creating microtip emitters. The technique of Henry Gray applies the microtip of
FIG. 2A
to form microtip emitters.
FIG. 4
is an illustration of a technique for creating microtip emitters. The technique of J. Itoh et al, of Electrotechnical lab Ibarake, Japan, utilizes a tetrode structure to form microtip emitters.
FIG. 5
is an illustration of a technique for creating microtip emitters. The technique of Kanamaru et al of Electrotechnical lab Ibarake, Japan, utilizes a two-stage photolithography and lift-off process with Reactive Ion Etching (RIE). The resulting wedges may be used as field tip emitters.
FIG. 6
is an illustration of a technique for creating a wedge emitter. The technique of J. G Flemming et al forms wedge shaped emitters.
FIG. 7
is an illustration of a prior art technique for creating microtip emitters. The technique of Li et al East China Normal University utilizes an oxidation and pattern-transfer process to form microtips.
FIG. 8
is an illustration of an application for microtip emitters. Field Emission (FE) flat panel displays have been created using microtip emitters. FE flat panel displays incorporating prior art microtip emitters generally require separate formation processes for the emitter tip and the emitter device.
Each of the above methods involves a multi-step process that requires special process conditions and is expensive. Additionally, the above methods do not easily allow multiple emission structures to be aligned in arrays with reliable uniformity, or the formation of different emitter geometries using one process. Finally, the above designs for field emission electron emitters are complex physical implementations with multiple components, again leading to high manufacturing costs and unreliable performance. Field emission electron emitters have a number of potential uses that are rendered impractical by the high cost, inherently low yield and difficulty of single-crystal design and fabrication.
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PCT US02/07176, International Search Report, Apr. 11, 2003.
Adibi-rizi Farshid
Huff Brett E.
Karpenko Oleh
Maxim Michael A.
Guharay Karabi
Intel Corporation
Patel Nimeshkumar D.
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