Design structure for SRAM active write assist for improved...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S189090, C365S230060

Reexamination Certificate

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07738283

ABSTRACT:
A design structure embodied in a machine-readable medium used in a design process is provided. The design structure comprises a static random access memory (“SRAM”), including a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operable to temporarily raise a voltage level of a low voltage reference to cells belonging to a column selected for writing from the plurality of columns, wherein the voltage control circuit includes a first n-type field effect transistor (“NFET”) and a second NFET, the first NFET having a conduction path connected between ground and the low voltage reference, the second NFET having a conduction path connected between a power supply and the low voltage reference.

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K. Zhang et al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,”2005 IEEE International Solid-State Circuits Conference, IEEE, pp. 474-475, 611 (Feb. 9, 2005).

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