Design structure for monitoring cross chip delay variation...

Details Design structure for monitoring cross chip delay variation... Design structure for monitoring cross chip delay variation...

2008-04-01

2009-02-03

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07487487

ABSTRACT:
A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a “schmoo plot” by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.

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