Design structure for high speed differential receiver with...

Details Design structure for high speed differential receiver with... Design structure for high speed differential receiver with...

2007-10-09

2009-02-17

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S117000

Reexamination Certificate

active

07492191

ABSTRACT:
A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

REFERENCES:
patent: 7043674 (2006-05-01), Rearick et al.
patent: 7068077 (2006-06-01), Reinschmidt

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