Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-04
2011-01-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C712S214000
Reexamination Certificate
active
07865862
ABSTRACT:
A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.
REFERENCES:
patent: 5361373 (1994-11-01), Gilson
patent: 5430734 (1995-07-01), Gilson
patent: 5600845 (1997-02-01), Gilson
patent: 5752035 (1998-05-01), Trimberger
patent: 6230307 (2001-05-01), Davis et al.
patent: 6590942 (2003-07-01), Hessel et al.
patent: 6622233 (2003-09-01), Gilson
patent: 6634023 (2003-10-01), Komatsu et al.
patent: 6862563 (2005-03-01), Hakewill et al.
patent: 6961842 (2005-11-01), Baxter
patent: 6983456 (2006-01-01), Poznanovic et al.
patent: 7028107 (2006-04-01), Yorbach et al.
patent: 7051185 (2006-05-01), Gilson
patent: 7127616 (2006-10-01), Kaneko
patent: 7269738 (2007-09-01), Kivimaki
patent: 7373631 (2008-05-01), Yuan et al.
patent: 7389487 (2008-06-01), Chan et al.
patent: 2001/0034876 (2001-10-01), Panchul et al.
patent: 2004/0049653 (2004-03-01), Gilson
patent: 2005/0120341 (2005-06-01), Blumenthal et al.
patent: 2006/0236292 (2006-10-01), Delp et al.
patent: 2008/0300851 (2008-12-01), Chakrabarti et al.
patent: 2009/0031111 (2009-01-01), Chou et al.
“Dynamically Reconfigureable Computing: A Novel Computation Technology with Potential to Improve National Security Capabilities by Dramatically Improving High-End Computing”, Ward et al., May 15, 2003.
“Reconfigurable Processor Architectures”, Ian Page, Oxford University Computing Laboratory.
“A Reconfigurable Computing Model for Biological Research Application of Smith-Waterman Analysis in Bacterial Genomes”, Collaboration with National Cancer Institiute—Frederick and SAIC Frederick.
Chou Deanna J.
Craig Jesse E.
Sargis, Jr. John
Singley Daneyand J.
Ventrone Sebastian T.
Cantor & Colburn LLP
International Business Machines - Corporation
LeStrange Michael
Siek Vuthe
LandOfFree
Design structure for dynamically selecting compiled... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Design structure for dynamically selecting compiled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design structure for dynamically selecting compiled... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2714734