Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-11-05
2009-11-24
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C327S156000, C327S157000, C327S158000, C327S159000, C327S155000
Reexamination Certificate
active
07622946
ABSTRACT:
A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
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Abadeer Wagdi W.
Hsu Louis Lu-Chen
Mandelman Jack A.
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Tabler Matthew C
Tan Vibol
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