Design structure for a redundant micro-loop structure for...

Details Design structure for a redundant micro-loop structure for... Design structure for a redundant micro-loop structure for...

2011-07-19

2011-07-19

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Layout generation

C716S054000, C716S056000, C716S119000, C716S126000, C716S130000, C257S773000, C257S774000, C257S775000, C438S618000

Reexamination Certificate

active

07984394

ABSTRACT:
A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

REFERENCES:
patent: 2003/0067075 (2003-04-01), Fukasawa
patent: 2008/0097738 (2008-04-01), Anderson et al.
patent: 2008/0142975 (2008-06-01), Ning
patent: 2008/0150149 (2008-06-01), Anderson et al.
“Tutorial—Cadence Design Environment”, by Antonio J. Lopez Martin, Klipsch School of Electrical and Computer Engineering, New Mexico State University, http://www.ece.nmsu.edu/vlsi/cadence/CADENCE%20Manual.pdf, @ Oct. 2002.
Yield Improvement by Local Wiring Redundancy, by Jeanne Bickford, Markus Buhler, Jason Hibbeler, Jurgen Koehl, Dirk Muller, Sven Peyer, Christian Schulte, IEEE Computer Society. Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED '06), 0-7695-2523-7/06.
U.S. Appl. No. 11/552,225, filed Oct. 24, 2006, titled “Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same,” Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak.
Related U.S. Appl. No. 12/045,374 filed Mar. 10, 2008, titled “Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process and Method of Forming the Same.”
Ex Parte Quayle Office Action dated Sep. 23, 2010 in related U.S. Appl. No. 12/045,374, titled “Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process and Method of Forming the Same.”
Response to Ex Parte Quayle Office Action dated Dec. 6, 2010 in related U.S. Appl. No. 12/045,374, titled “Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process and Method of Forming the Same.”
Notice of Allowance dated Feb. 7, 2011 in related U.S. Appl. No. 12/045,374, titled “Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process and Method of Forming the Same.”
Amendment Under 37 CFR 1.312 dated Feb. 15, 2011 in related U.S. Appl. No. 12/045,374, titled “Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process and Method of Forming the Same.”

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